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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: Featured Reference Designs

    Started by mmatheson, 16th June 2016 22:04
    • Replies: 0
    • Views: 6,713
    16th June 2016, 22:04 Go to last post
  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 25,854
    3rd December 2007, 18:00 Go to last post
  1. 7nm nmos with level 54

    Started by GayatriGaikwad, Yesterday 12:22
    • Replies: 2
    • Views: 244
    Today, 18:56 Go to last post
  2. Moved: Wondering about a good external IC watchdog

    Started by flote21, Today 08:41
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  3. Moved: 7nm nmos with 54 level

    Started by GayatriGaikwad, Today 07:03
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    • Replies: 6
    • Views: 660
    Yesterday, 19:29 Go to last post
  4. [SOLVED] PTM-MG hspice model for finfet

    Started by Bakr.hesham, 18th June 2017 14:18
    • Replies: 7
    • Views: 1,019
    Yesterday, 18:08 Go to last post
    • Replies: 0
    • Views: 114
    Yesterday, 11:59 Go to last post
  5. Effect of high temperature on cntfet

    Started by tejashrimane, Yesterday 08:30
    • Replies: 1
    • Views: 151
    Yesterday, 10:12 Go to last post
  6. Triple pole analog switch by cmos ?

    Started by Electric_Shock, 17th November 2017 09:33
    • Replies: 2
    • Views: 466
    21st November 2017, 19:26 Go to last post
  7. Moved: Leakage current and mobility in hspice

    Started by GayatriGaikwad, 21st November 2017 22:59
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  8. High Voltage Technology file

    Started by deardeepa76, 31st October 2017 08:07
    • Replies: 5
    • Views: 1,128
    21st November 2017, 14:10 Go to last post
  9. Dummy Generation in Cadence

    Started by bio_man, 11th November 2017 18:43
    • Replies: 15
    • Views: 3,051
    20th November 2017, 16:03 Go to last post
  10. Gain and stability of fully differential Amplifiers

    Started by hannover90, 15th November 2017 21:56
    • Replies: 9
    • Views: 1,559
    17th November 2017, 16:58 Go to last post
  11. Moved: 5v POWER SUPPLY PROBLEM

    Started by dp1311.dp, 17th November 2017 11:59
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  12. Split Attenuating Cap SAR ADC problem

    Started by elx, 15th November 2017 03:27
    • Replies: 1
    • Views: 639
    15th November 2017, 04:53 Go to last post
  13. Converting Layout in Cadence Virtuoso to GDSII format

    Started by bio_man, 7th November 2017 15:20
    • Replies: 10
    • Views: 1,370
    11th November 2017, 18:45 Go to last post
  14. [SOLVED] Fully Differential Amplifier and output common-mode voltage

    Started by hannover90, 9th November 2017 21:16
    • Replies: 5
    • Views: 1,043
    10th November 2017, 19:42 Go to last post
  15. [SOLVED] Split Attenuation Cap DAC

    Started by elx, 10th November 2017 04:31
    • Replies: 1
    • Views: 659
    10th November 2017, 07:33 Go to last post
  16. [SOLVED] Seal ring stretch help

    Started by kahroba92, 8th November 2017 22:05
    • Replies: 8
    • Views: 868
    10th November 2017, 02:30 Go to last post
  17. Biasing a common-mode level for differential pair

    Started by Electric_Shock, 9th November 2017 05:30
    • Replies: 1
    • Views: 374
    10th November 2017, 02:15 Go to last post
  18. Shielding for the MIM capacitor

    Started by shanmei, 4th November 2017 15:46
    • Replies: 6
    • Views: 973
    10th November 2017, 01:56 Go to last post
  19. Simulating the designed circuit in Tanner EDA

    Started by selvashaashi, 9th November 2017 10:52
    • Replies: 1
    • Views: 365
    10th November 2017, 01:50 Go to last post
  20. Couldn't plot dc gain in cadence

    Started by shanmathi, 1st November 2017 16:02
    • Replies: 4
    • Views: 1,094
    10th November 2017, 01:47 Go to last post
  21. Hspice waveform problem

    Started by an_82, 9th November 2017 06:45
    • Replies: 3
    • Views: 504
    10th November 2017, 01:45 Go to last post
  22. Moved: bizzare buffer AC response

    Started by mburakbaran, 8th November 2017 18:36
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  23. How to build a simple MOSFET model

    Started by CAMALEAO, 8th November 2017 08:33
    • Replies: 1
    • Views: 502
    8th November 2017, 17:00 Go to last post
  24. Low power op amp in subthreshold region

    Started by sreelekshmivipin, 23rd October 2017 10:56
    • Replies: 3
    • Views: 1,040
    8th November 2017, 16:37 Go to last post
  25. Core layout separation from IO pads

    Started by saha.123, 25th October 2017 07:10
    • Replies: 3
    • Views: 730
    8th November 2017, 15:47 Go to last post
  26. Moved: Modified PMOS Load Circuitry

    Started by promach, 7th November 2017 12:37
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  27. [SOLVED] LVS weird problem in Cadence

    Started by bio_man, 6th November 2017 00:14
    • Replies: 5
    • Views: 782
    7th November 2017, 14:47 Go to last post