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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: Featured Reference Designs

    Started by mmatheson, 16th June 2016 22:04
    • Replies: 0
    • Views: 4,794
    16th June 2016, 22:04 Go to last post
  2. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 23,928
    3rd December 2007, 18:00 Go to last post
  1. Inductor layout design in Cadence Virtuoso

    Started by Vijay Vinay, 21st August 2017 13:59
    • Replies: 7
    • Views: 269
    Yesterday, 21:01 Go to last post
  2. Gyrator implementation of chip inductor

    Started by promach, 24th June 2017 15:30
    3 Pages
    1 2 3
    • Replies: 44
    • Views: 3,728
    Yesterday, 09:05 Go to last post
  3. Difference between "PTUB" and "P-WELL"

    Started by CubeSquared, 7th August 2017 14:55
    • Replies: 3
    • Views: 534
    Yesterday, 07:58 Go to last post
  4. Flip Chip Layout Requirements

    Started by krrao, Yesterday 07:55
    • Replies: 0
    • Views: 53
    Yesterday, 07:55 Go to last post
  5. Post layout simulation and parasitic extraction

    Started by bio_man, 9th August 2017 17:07
    • Replies: 16
    • Views: 799
    Yesterday, 00:56 Go to last post
  6. Moved: Phase noise increases with reduction in oscillation frequency

    Started by venn_ng, 20th August 2017 17:57
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  7. Load Capacitance Calculation

    Started by samster19, 18th August 2017 17:32
    • Replies: 4
    • Views: 385
    20th August 2017, 17:38 Go to last post
  8. Moved: Digital phase locked loop

    Started by hanikapa, 19th August 2017 20:28
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    • Replies: 10
    • Views: 406
    18th August 2017, 20:44 Go to last post
    • Replies: 1
    • Views: 232
    17th August 2017, 18:37 Go to last post
  9. Determine Technology Current using foundry models

    Started by deveshkm, 9th August 2017 08:03
    • Replies: 7
    • Views: 468
    17th August 2017, 14:21 Go to last post
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  10. Moved: Dynamic range of amplifiers

    Started by mordak, 16th August 2017 23:50
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    • Replies: 4
    • Views: 313
    16th August 2017, 22:20 Go to last post
  11. Moved: How to use data driven piecewise linear source in hspice

    Started by GoldenCheese, 16th August 2017 07:10
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  12. Hi can any one explain circular symmetry matching?

    Started by harsha08, 16th August 2017 06:03
    • Replies: 0
    • Views: 171
    16th August 2017, 06:03 Go to last post
  13. Gate fingering in clocked comparators

    Started by bio_man, 14th August 2017 21:58
    • Replies: 2
    • Views: 245
    15th August 2017, 05:07 Go to last post
  14. [Moved]: Guard Ring / Well Tie for a dc test circuit

    Started by nkp6195, 15th August 2017 00:09
    • Replies: 2
    • Views: 226
    15th August 2017, 01:49 Go to last post
  15. how to show Net names in Cadence Layout

    Started by bio_man, 14th August 2017 17:35
    • Replies: 3
    • Views: 261
    15th August 2017, 00:37 Go to last post
    • Replies: 8
    • Views: 440
    14th August 2017, 16:18 Go to last post
  16. Moved: CA3140AE Op amplifier ic

    Started by omerysmi, 12th August 2017 13:20
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  17. Moved: saed-90nm library files

    Started by jmaileh.b, 10th August 2017 07:57
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    • Replies: 9
    • Views: 500
    10th August 2017, 06:59 Go to last post
  18. Missing instance discrepancy

    Started by Vijay Vinay, 8th August 2017 16:58
    • Replies: 9
    • Views: 576
    9th August 2017, 18:43 Go to last post
  19. What is b11hfc technology

    Started by Vijay Vinay, 1st August 2017 17:13
    • Replies: 3
    • Views: 567
    9th August 2017, 15:00 Go to last post
    • Replies: 3
    • Views: 366
    9th August 2017, 08:20 Go to last post
  20. change grid setting using skill programing

    Started by iqbalsahid, 1st August 2017 11:26
    • Replies: 8
    • Views: 727
    8th August 2017, 13:57 Go to last post
  21. Quality factor of inductor

    Started by promach, 5th August 2017 09:18
    • Replies: 12
    • Views: 1,023
    8th August 2017, 11:22 Go to last post
  22. final steps to produce GDSII file for fabrication

    Started by zyadzezo, 5th August 2017 02:34
    • Replies: 1
    • Views: 385
    5th August 2017, 15:11 Go to last post
  23. Moved: 2nd order SDM followed by sinc2 decimation filter?

    Started by neoflash, 4th August 2017 19:38
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