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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 18,202
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 25,073
    21st March 2007, 21:21 Go to last post
    • Replies: 15
    • Views: 592
    Today, 07:35 Go to last post
  1. Atmel/Microchip ATF750 series programmer???

    Started by whack, 20th June 2017 15:50
    • Replies: 2
    • Views: 297
    Yesterday, 17:22 Go to last post
  2. reading from w5300 registers

    Started by farzaneh_2561, Yesterday 08:22
    • Replies: 6
    • Views: 191
    Yesterday, 17:06 Go to last post
  3. How compare between between mesh and torus?

    Started by Reeyam, Yesterday 11:10
    • Replies: 0
    • Views: 70
    Yesterday, 11:10 Go to last post
  4. bitwise function description

    Started by Binome, 27th June 2017 16:22
    • Replies: 6
    • Views: 374
    Yesterday, 10:23 Go to last post
  5. First Design with Quartus Prime

    Started by zionico90, 26th June 2017 14:54
    • Replies: 3
    • Views: 165
    Yesterday, 07:28 Go to last post
  6. [SOLVED] How to have an undefined range in function?

    Started by wesleytaylor, 26th June 2017 13:49
    • Replies: 3
    • Views: 331
    27th June 2017, 10:09 Go to last post
  7. Real life throughput of FPGA DSP blocks

    Started by shaiko, 24th June 2017 15:15
    • Replies: 10
    • Views: 566
    27th June 2017, 04:56 Go to last post
  8. Reading numbers and assign them to an array

    Started by mahmood.n, 23rd June 2017 10:48
    • Replies: 13
    • Views: 876
    25th June 2017, 18:55 Go to last post
    • Replies: 6
    • Views: 572
    22nd June 2017, 11:28 Go to last post
    • Replies: 1
    • Views: 163
    22nd June 2017, 11:24 Go to last post
    • Replies: 3
    • Views: 237
    22nd June 2017, 10:03 Go to last post
    • Replies: 2
    • Views: 224
    22nd June 2017, 06:29 Go to last post
  9. 4 to 11 Decoder in VerilogA

    Started by PaulineVi, 21st June 2017 14:59
    • Replies: 6
    • Views: 364
    21st June 2017, 18:58 Go to last post
  10. matrix array from instantiations

    Started by nizdom, 21st June 2017 10:33
    • Replies: 1
    • Views: 229
    21st June 2017, 16:07 Go to last post
  11. VHDL Comparison Tree

    Started by shaiko, 18th June 2017 17:48
    • Replies: 18
    • Views: 1,158
    21st June 2017, 07:56 Go to last post
  12. USB blaster fail to work after Quartus update

    Started by mahmood.n, 20th June 2017 16:48
    • Replies: 3
    • Views: 414
    20th June 2017, 23:56 Go to last post
    • Replies: 1
    • Views: 235
    20th June 2017, 14:46 Go to last post
  13. send/receive data to/from fpga device

    Started by mahmood.n, 16th June 2017 09:24
    • Replies: 11
    • Views: 945
    17th June 2017, 09:32 Go to last post
  14. How to avoid using clock trees in Zynq FPGAs?

    Started by msdarvishi, 15th June 2017 00:35
    • Replies: 4
    • Views: 478
    17th June 2017, 00:47 Go to last post
    • Replies: 4
    • Views: 324
    17th June 2017, 00:42 Go to last post
  15. Single multiplier takes up a whole DSP block for

    Started by shaiko, 14th June 2017 15:51
    • Replies: 13
    • Views: 802
    16th June 2017, 08:54 Go to last post
  16. Quartus not show the port size correctly

    Started by mahmood.n, 15th June 2017 23:12
    • Replies: 2
    • Views: 431
    16th June 2017, 07:43 Go to last post
  17. simulation-based faults injection

    Started by ouij, 12th June 2017 11:23
    • Replies: 7
    • Views: 579
    15th June 2017, 15:41 Go to last post
  18. binary dividing: restoring method

    Started by kk_0, 13th June 2017 20:32
    • Replies: 3
    • Views: 467
    14th June 2017, 22:22 Go to last post
    • Replies: 3
    • Views: 708
    14th June 2017, 18:01 Go to last post
  19. PWM for LED module to choose duty cycle

    Started by manush30, 28th May 2017 14:22
    • Replies: 6
    • Views: 833
    14th June 2017, 17:34 Go to last post
  20. Synthesis: Check_Design Report too many warnings

    Started by Johannah, 13th June 2017 08:48
    • Replies: 3
    • Views: 281
    14th June 2017, 15:41 Go to last post