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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 22,430
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 28,197
    21st March 2007, 21:21 Go to last post
  1. Mapping block RAMs to specific address space

    Started by sajjad.hussain, 23rd November 2017 00:08
    • Replies: 4
    • Views: 857
    Yesterday, 16:49 Go to last post
  2. Asynchronous fifo cdc question

    Started by promach, 21st November 2017 06:51
    • Replies: 1
    • Views: 253
    Yesterday, 02:00 Go to last post
    • Replies: 0
    • Views: 517
    23rd November 2017, 05:26 Go to last post
  3. Error in verilog code

    Started by josephine1234, 21st November 2017 07:25
    • Replies: 5
    • Views: 530
    22nd November 2017, 22:22 Go to last post
    • Replies: 1
    • Views: 173
    22nd November 2017, 16:34 Go to last post
  4. [SOLVED] IOBUF primative doesn't behave the way i want

    Started by wesleytaylor, 21st November 2017 16:25
    • Replies: 3
    • Views: 607
    22nd November 2017, 14:31 Go to last post
  5. MachXO2 DDR and PCLK routing issue

    Started by juanMco, 20th November 2017 17:32
    • Replies: 4
    • Views: 646
    21st November 2017, 17:48 Go to last post
  6. MAX10 PLL External Clock Output

    Started by Yorki, 9th November 2017 14:35
    • Replies: 7
    • Views: 742
    21st November 2017, 09:55 Go to last post
  7. FPGA interface with 100Mbps Ethernet

    Started by fouwad, 17th November 2017 07:10
    • Replies: 3
    • Views: 977
    20th November 2017, 14:26 Go to last post
  8. Help tracking down very long synthesis time

    Started by whaleeee, 13th November 2017 19:51
    • Replies: 13
    • Views: 1,345
    20th November 2017, 08:48 Go to last post
  9. [SOLVED] concurrent vhdl code generating latches

    Started by rafimiet, 19th November 2017 10:10
    • Replies: 4
    • Views: 692
    19th November 2017, 11:43 Go to last post
  10. [moved] ZedBoard HDMI input without FMC card

    Started by DilshanSampath, 17th November 2017 18:13
    • Replies: 2
    • Views: 527
    18th November 2017, 20:02 Go to last post
  11. Moving window integrator

    Started by Rani1234, 17th November 2017 12:43
    • Replies: 4
    • Views: 445
    17th November 2017, 18:38 Go to last post
  12. [SOLVED] Initializing Xilinx BRAM with image pixels

    Started by Taki_comp, 6th November 2017 20:52
    • Replies: 10
    • Views: 1,174
    17th November 2017, 14:38 Go to last post
  13. FIR band pass filter using verilog

    Started by josephine1234, 17th November 2017 10:30
    • Replies: 6
    • Views: 409
    17th November 2017, 11:05 Go to last post
  14. Xilinx ISE - readmemh system task taking too much time

    Started by NikosTS, 14th November 2017 11:36
    • Replies: 1
    • Views: 358
    17th November 2017, 07:11 Go to last post
    • Replies: 1
    • Views: 510
    16th November 2017, 17:04 Go to last post
  15. VHDL coding techniques

    Started by manishpatkar, 13th November 2017 12:55
    • Replies: 16
    • Views: 1,119
    16th November 2017, 15:01 Go to last post
  16. Missing JESD parameters in Xilinx JESD204 IP Rx!!

    Started by samg, 15th November 2017 05:46
    • Replies: 2
    • Views: 440
    15th November 2017, 11:31 Go to last post
    • Replies: 5
    • Views: 613
    14th November 2017, 23:20 Go to last post
    • Replies: 1
    • Views: 290
    14th November 2017, 18:17 Go to last post
  17. Sending data sequentially

    Started by beginner_EDA, 8th November 2017 12:42
    • Replies: 6
    • Views: 607
    14th November 2017, 13:24 Go to last post
    • Replies: 3
    • Views: 851
    13th November 2017, 21:38 Go to last post
    • Replies: 3
    • Views: 1,020
    13th November 2017, 12:00 Go to last post
  18. Configuring JESD parameters in Xilinx JESD204

    Started by samg, 13th November 2017 07:01
    • Replies: 0
    • Views: 430
    13th November 2017, 07:01 Go to last post
    • Replies: 1
    • Views: 879
    11th November 2017, 13:03 Go to last post
  19. [SOLVED] Programmable Priority Encoder

    Started by RatedR, 13th July 2017 17:00
    2 Pages
    1 2
    • Replies: 31
    • Views: 3,695
    10th November 2017, 17:33 Go to last post
  20. Moved: IGMP Packet generating software

    Started by beginner_EDA, 10th November 2017 16:10
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    •  
    • Replies: 12
    • Views: 1,438
    9th November 2017, 20:04 Go to last post