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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 19,601
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 26,091
    21st March 2007, 21:21 Go to last post
  1. FPGA asic design tools

    Started by flo, Yesterday 20:28
    • Replies: 3
    • Views: 247
    Today, 13:25 Go to last post
  2. High Level employment of the "imply" operator

    Started by BrownBear1968, 17th August 2017 21:55
    • Replies: 6
    • Views: 543
    18th August 2017, 22:32 Go to last post
  3. Tcl to update version number

    Started by wesleytaylor, 18th August 2017 13:04
    • Replies: 1
    • Views: 120
    18th August 2017, 15:14 Go to last post
    • Replies: 10
    • Views: 825
    17th August 2017, 21:22 Go to last post
  4. saving the the content of a nios2 console.

    Started by dipin, 17th August 2017 10:06
    • Replies: 0
    • Views: 165
    17th August 2017, 10:06 Go to last post
    • Replies: 3
    • Views: 368
    16th August 2017, 11:31 Go to last post
    • Replies: 5
    • Views: 180
    15th August 2017, 19:39 Go to last post
  5. Spartan - 3A ADC and DAC interface not working

    Started by NJ176, 15th August 2017 10:22
    • Replies: 6
    • Views: 180
    15th August 2017, 15:16 Go to last post
  6. a logic to detect FPGA family?

    Started by Port Map, 13th August 2017 10:42
    • Replies: 8
    • Views: 346
    15th August 2017, 09:31 Go to last post
  7. synchronize data with general GPIO clk

    Started by nsgil85, 13th August 2017 11:27
    • Replies: 8
    • Views: 386
    14th August 2017, 15:59 Go to last post
    • Replies: 5
    • Views: 415
    12th August 2017, 20:54 Go to last post
    • Replies: 5
    • Views: 221
    12th August 2017, 13:59 Go to last post
  8. How to snyc one 7 Series Transceiver to anothe

    Started by beginner_EDA, 11th August 2017 13:42
    • Replies: 3
    • Views: 258
    12th August 2017, 09:32 Go to last post
  9. how to fix WARNING:Xst:1710

    Started by tanish, 12th August 2017 08:07
    • Replies: 1
    • Views: 169
    12th August 2017, 08:42 Go to last post
  10. optimized CDR settings for 12G-SDI

    Started by beginner_EDA, 10th August 2017 09:58
    • Replies: 1
    • Views: 243
    11th August 2017, 15:56 Go to last post
  11. VHDL Instantiation in modelSim

    Started by hareeshP, 10th August 2017 06:57
    • Replies: 14
    • Views: 430
    10th August 2017, 19:16 Go to last post
  12. Cannot Read Data in 1-Port RAM IP Core

    Started by learni, 10th August 2017 09:40
    • Replies: 2
    • Views: 245
    10th August 2017, 18:52 Go to last post
  13. ADC and DAC interface for Spartan - 3A

    Started by NJ176, 10th August 2017 11:02
    • Replies: 1
    • Views: 198
    10th August 2017, 13:13 Go to last post
  14. Cyclone IV learning board

    Started by andrew_que, 8th August 2017 16:26
    • Replies: 3
    • Views: 408
    9th August 2017, 11:33 Go to last post
    • Replies: 10
    • Views: 846
    9th August 2017, 06:27 Go to last post
  15. Same constant name in 2 different packages

    Started by shaiko, 5th August 2017 12:53
    • Replies: 11
    • Views: 908
    7th August 2017, 10:23 Go to last post
  16. FPGA timing due to Dist ram

    Started by Alauddin123, 6th August 2017 10:42
    • Replies: 1
    • Views: 368
    6th August 2017, 12:08 Go to last post
  17. use C to program FPGA

    Started by matin-kh, 2nd July 2017 12:39
    • Replies: 11
    • Views: 1,785
    4th August 2017, 23:04 Go to last post
  18. substitution for loops in design compiler

    Started by moonshine8995, 4th August 2017 11:04
    • Replies: 4
    • Views: 604
    4th August 2017, 18:02 Go to last post
  19. Amp ADC interfacing using VHDL for Spartan-3A

    Started by NJ176, 31st July 2017 09:44
    • Replies: 4
    • Views: 731
    4th August 2017, 17:49 Go to last post
  20. [SOLVED] xilinx timing analyze using modelsim SE

    Started by tanish, 3rd August 2017 17:53
    • Replies: 1
    • Views: 565
    3rd August 2017, 20:53 Go to last post
    • Replies: 2
    • Views: 443
    3rd August 2017, 16:31 Go to last post
  21. Programmable Priority Encoder

    Started by RatedR, 13th July 2017 17:00
    • Replies: 10
    • Views: 1,159
    3rd August 2017, 08:25 Go to last post
  22. Verilog Assignment code

    Started by hareeshP, 1st August 2017 10:23
    • Replies: 4
    • Views: 715
    2nd August 2017, 06:45 Go to last post