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Threads 1 to 30 of 22011

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 22,820
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 28,586
    21st March 2007, 21:21 Go to last post
  1. Scope of STA in FPGAs

    Started by hareesh007, 16th December 2017 13:26
    • Replies: 3
    • Views: 134
    Today, 03:49 Go to last post
  2. Overcoming the 8:1 width conversion problem

    Started by shaiko, Yesterday 19:14
    • Replies: 2
    • Views: 94
    Yesterday, 23:57 Go to last post
  3. Closed: help regarding fpga implemetation

    Started by kumar1988, 2nd September 2013 18:01
    • Replies: 5
    • Views: 530
    Yesterday, 18:07 Go to last post
  4. Vivado HLS Experience

    Started by MarkPh, 1st December 2017 15:58
    • Replies: 4
    • Views: 663
    Yesterday, 12:11 Go to last post
  5. FPGA Based Car Game (Christmas Themed)

    Started by bwarlord01, 16th December 2017 15:26
    • Replies: 1
    • Views: 224
    16th December 2017, 19:46 Go to last post
  6. AXI 4 Stream Data Width Converter

    Started by Vlad., 13th December 2017 08:22
    • Replies: 9
    • Views: 447
    16th December 2017, 03:01 Go to last post
  7. Vivado - math.real support

    Started by shaiko, 14th December 2017 12:37
    • Replies: 7
    • Views: 273
    15th December 2017, 13:12 Go to last post
  8. Changing IP parameters in Vivado using HDL generics

    Started by shaiko, 13th December 2017 15:30
    • Replies: 8
    • Views: 249
    14th December 2017, 11:14 Go to last post
  9. SSD performance gain

    Started by shaiko, 12th December 2017 17:27
    • Replies: 7
    • Views: 410
    14th December 2017, 09:45 Go to last post
  10. OpenCL GPU vs FPGA implementation

    Started by shaiko, 13th December 2017 01:23
    • Replies: 1
    • Views: 234
    13th December 2017, 16:35 Go to last post
  11. Generate desired random number in range in verilog

    Started by tayyab786, 27th November 2017 20:14
    2 Pages
    1 2
    • Replies: 20
    • Views: 1,997
    11th December 2017, 23:48 Go to last post
  12. FPGA USB Data software

    Started by expertengr, 9th December 2017 12:10
    • Replies: 5
    • Views: 532
    11th December 2017, 19:52 Go to last post
  13. Moved: ZYNQ USB OTG Data Transfer

    Started by expertengr, 11th December 2017 23:59
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  14. [SOLVED] Round robin arbiter with ring counter.

    Started by ppko1233, 10th December 2017 14:26
    • Replies: 1
    • Views: 270
    11th December 2017, 16:48 Go to last post
  15. Simulation time in simulation tools like ISIM/model sim

    Started by mjuneja, 5th December 2017 08:25
    • Replies: 5
    • Views: 518
    11th December 2017, 12:48 Go to last post
  16. Improve UART resource usage

    Started by promach, 10th December 2017 12:41
    • Replies: 1
    • Views: 281
    11th December 2017, 02:09 Go to last post
  17. [SOLVED] logic : give value in which require decimal number represent

    Started by tayyab786, 10th December 2017 14:05
    • Replies: 5
    • Views: 342
    10th December 2017, 22:10 Go to last post
  18. Moved: range of lfsr depend upon input value

    Started by tayyab786, 10th December 2017 22:17
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  19. Circuit protection with VHDL code

    Started by manush30, 6th December 2017 08:40
    • Replies: 9
    • Views: 611
    10th December 2017, 10:54 Go to last post
  20. ADS (advanced Design System) Xilinx FPGA model kit

    Started by Enrocinu, 10th December 2017 00:00
    • Replies: 0
    • Views: 355
    10th December 2017, 00:00 Go to last post
    • Replies: 2
    • Views: 288
    9th December 2017, 20:11 Go to last post
    • Replies: 4
    • Views: 715
    9th December 2017, 16:34 Go to last post
  21. Altera Stratix 10 Hyper-Registers

    Started by Wiljan, 9th December 2017 14:24
    • Replies: 0
    • Views: 271
    9th December 2017, 14:24 Go to last post
  22. choosing high speed data storage element

    Started by amin5659, 7th December 2017 16:42
    • Replies: 10
    • Views: 626
    9th December 2017, 10:39 Go to last post
  23. [SOLVED] How to load program to A54SX16A-PQG208M FPGA?

    Started by Mithun_K_Das, 5th December 2017 12:17
    • Replies: 13
    • Views: 1,007
    9th December 2017, 05:34 Go to last post
    • Replies: 4
    • Views: 385
    8th December 2017, 22:19 Go to last post
  24. How to run two module in series using verilog

    Started by kapaa, 7th December 2017 03:21
    • Replies: 6
    • Views: 559
    7th December 2017, 22:44 Go to last post
  25. FPGA-Based Christmas project

    Started by bwarlord01, 6th December 2017 19:29
    • Replies: 3
    • Views: 482
    7th December 2017, 02:46 Go to last post