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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 19,532
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 26,040
    21st March 2007, 21:21 Go to last post
    • Replies: 1
    • Views: 68
    Today, 00:28 Go to last post
    • Replies: 10
    • Views: 764
    Yesterday, 21:22 Go to last post
  1. saving the the content of a nios2 console.

    Started by dipin, Yesterday 10:06
    • Replies: 0
    • Views: 112
    Yesterday, 10:06 Go to last post
    • Replies: 3
    • Views: 324
    16th August 2017, 11:31 Go to last post
    • Replies: 5
    • Views: 141
    15th August 2017, 19:39 Go to last post
  2. Spartan - 3A ADC and DAC interface not working

    Started by NJ176, 15th August 2017 10:22
    • Replies: 6
    • Views: 144
    15th August 2017, 15:16 Go to last post
  3. a logic to detect FPGA family?

    Started by Port Map, 13th August 2017 10:42
    • Replies: 8
    • Views: 293
    15th August 2017, 09:31 Go to last post
  4. synchronize data with general GPIO clk

    Started by nsgil85, 13th August 2017 11:27
    • Replies: 8
    • Views: 334
    14th August 2017, 15:59 Go to last post
    • Replies: 5
    • Views: 380
    12th August 2017, 20:54 Go to last post
    • Replies: 5
    • Views: 189
    12th August 2017, 13:59 Go to last post
  5. How to snyc one 7 Series Transceiver to anothe

    Started by beginner_EDA, 11th August 2017 13:42
    • Replies: 3
    • Views: 227
    12th August 2017, 09:32 Go to last post
  6. how to fix WARNING:Xst:1710

    Started by tanish, 12th August 2017 08:07
    • Replies: 1
    • Views: 140
    12th August 2017, 08:42 Go to last post
  7. optimized CDR settings for 12G-SDI

    Started by beginner_EDA, 10th August 2017 09:58
    • Replies: 1
    • Views: 211
    11th August 2017, 15:56 Go to last post
  8. VHDL Instantiation in modelSim

    Started by hareeshP, 10th August 2017 06:57
    • Replies: 14
    • Views: 398
    10th August 2017, 19:16 Go to last post
  9. Cannot Read Data in 1-Port RAM IP Core

    Started by learni, 10th August 2017 09:40
    • Replies: 2
    • Views: 208
    10th August 2017, 18:52 Go to last post
  10. ADC and DAC interface for Spartan - 3A

    Started by NJ176, 10th August 2017 11:02
    • Replies: 1
    • Views: 167
    10th August 2017, 13:13 Go to last post
  11. Cyclone IV learning board

    Started by andrew_que, 8th August 2017 16:26
    • Replies: 3
    • Views: 376
    9th August 2017, 11:33 Go to last post
    • Replies: 10
    • Views: 815
    9th August 2017, 06:27 Go to last post
  12. Same constant name in 2 different packages

    Started by shaiko, 5th August 2017 12:53
    • Replies: 11
    • Views: 871
    7th August 2017, 10:23 Go to last post
  13. FPGA timing due to Dist ram

    Started by Alauddin123, 6th August 2017 10:42
    • Replies: 1
    • Views: 337
    6th August 2017, 12:08 Go to last post
  14. use C to program FPGA

    Started by matin-kh, 2nd July 2017 12:39
    • Replies: 11
    • Views: 1,750
    4th August 2017, 23:04 Go to last post
  15. substitution for loops in design compiler

    Started by moonshine8995, 4th August 2017 11:04
    • Replies: 4
    • Views: 575
    4th August 2017, 18:02 Go to last post
  16. Amp ADC interfacing using VHDL for Spartan-3A

    Started by NJ176, 31st July 2017 09:44
    • Replies: 4
    • Views: 702
    4th August 2017, 17:49 Go to last post
  17. [SOLVED] xilinx timing analyze using modelsim SE

    Started by tanish, 3rd August 2017 17:53
    • Replies: 1
    • Views: 537
    3rd August 2017, 20:53 Go to last post
    • Replies: 2
    • Views: 414
    3rd August 2017, 16:31 Go to last post
  18. Programmable Priority Encoder

    Started by RatedR, 13th July 2017 17:00
    • Replies: 10
    • Views: 1,127
    3rd August 2017, 08:25 Go to last post
  19. Verilog Assignment code

    Started by hareeshP, 1st August 2017 10:23
    • Replies: 4
    • Views: 684
    2nd August 2017, 06:45 Go to last post
  20. VHDL Register transferring.

    Started by hareeshP, 19th July 2017 13:28
    • Replies: 15
    • Views: 984
    2nd August 2017, 06:15 Go to last post
  21. jtag uart speed problem

    Started by dipin, 1st August 2017 12:25
    • Replies: 1
    • Views: 546
    1st August 2017, 16:43 Go to last post