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Threads 1 to 30 of 22005

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 22,733
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 28,513
    21st March 2007, 21:21 Go to last post
  1. SSD performance gain

    Started by shaiko, Yesterday 17:27
    • Replies: 5
    • Views: 222
    Today, 09:26 Go to last post
  2. AXI 4 Stream Data Width Converter

    Started by Vlad., Today 08:22
    • Replies: 1
    • Views: 27
    Today, 08:33 Go to last post
  3. OpenCL GPU vs FPGA implementation

    Started by shaiko, Today 01:23
    • Replies: 0
    • Views: 94
    Today, 01:23 Go to last post
  4. Generate desired random number in range in verilog

    Started by tayyab786, 27th November 2017 20:14
    2 Pages
    1 2
    • Replies: 20
    • Views: 1,865
    11th December 2017, 23:48 Go to last post
  5. FPGA USB Data software

    Started by expertengr, 9th December 2017 12:10
    • Replies: 5
    • Views: 411
    11th December 2017, 19:52 Go to last post
  6. Moved: ZYNQ USB OTG Data Transfer

    Started by expertengr, 11th December 2017 23:59
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  7. [SOLVED] Round robin arbiter with ring counter.

    Started by ppko1233, 10th December 2017 14:26
    • Replies: 1
    • Views: 189
    11th December 2017, 16:48 Go to last post
  8. Simulation time in simulation tools like ISIM/model sim

    Started by mjuneja, 5th December 2017 08:25
    • Replies: 5
    • Views: 438
    11th December 2017, 12:48 Go to last post
  9. Improve UART resource usage

    Started by promach, 10th December 2017 12:41
    • Replies: 1
    • Views: 199
    11th December 2017, 02:09 Go to last post
  10. [SOLVED] logic : give value in which require decimal number represent

    Started by tayyab786, 10th December 2017 14:05
    • Replies: 5
    • Views: 256
    10th December 2017, 22:10 Go to last post
  11. Moved: range of lfsr depend upon input value

    Started by tayyab786, 10th December 2017 22:17
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  12. Circuit protection with VHDL code

    Started by manush30, 6th December 2017 08:40
    • Replies: 9
    • Views: 531
    10th December 2017, 10:54 Go to last post
  13. ADS (advanced Design System) Xilinx FPGA model kit

    Started by Enrocinu, 10th December 2017 00:00
    • Replies: 0
    • Views: 279
    10th December 2017, 00:00 Go to last post
    • Replies: 2
    • Views: 214
    9th December 2017, 20:11 Go to last post
    • Replies: 4
    • Views: 641
    9th December 2017, 16:34 Go to last post
  14. Altera Stratix 10 Hyper-Registers

    Started by Wiljan, 9th December 2017 14:24
    • Replies: 0
    • Views: 190
    9th December 2017, 14:24 Go to last post
  15. choosing high speed data storage element

    Started by amin5659, 7th December 2017 16:42
    • Replies: 10
    • Views: 522
    9th December 2017, 10:39 Go to last post
  16. [SOLVED] How to load program to A54SX16A-PQG208M FPGA?

    Started by Mithun_K_Das, 5th December 2017 12:17
    • Replies: 13
    • Views: 918
    9th December 2017, 05:34 Go to last post
    • Replies: 4
    • Views: 311
    8th December 2017, 22:19 Go to last post
  17. How to run two module in series using verilog

    Started by kapaa, 7th December 2017 03:21
    • Replies: 6
    • Views: 476
    7th December 2017, 22:44 Go to last post
  18. FPGA-Based Christmas project

    Started by bwarlord01, 6th December 2017 19:29
    • Replies: 3
    • Views: 406
    7th December 2017, 02:46 Go to last post
  19. What is Most Economic FPGA?

    Started by Zerox100, 5th December 2017 16:04
    • Replies: 2
    • Views: 361
    6th December 2017, 12:59 Go to last post
    • Replies: 0
    • Views: 216
    6th December 2017, 12:18 Go to last post
  20. Vendor specific macros for Igloo2

    Started by filip.amator, 5th December 2017 23:15
    • Replies: 2
    • Views: 470
    6th December 2017, 11:38 Go to last post
  21. ppg database regarding

    Started by josephine1234, 5th December 2017 12:00
    • Replies: 1
    • Views: 211
    5th December 2017, 12:13 Go to last post
  22. FPGA Ethernet interface

    Started by Vlad., 3rd December 2017 19:11
    • Replies: 3
    • Views: 1,096
    4th December 2017, 09:51 Go to last post
  23. Vivado HLS Experience

    Started by MarkPh, 1st December 2017 15:58
    • Replies: 2
    • Views: 550
    3rd December 2017, 07:48 Go to last post
  24. Regarding Verilog codes

    Started by josephine1234, 1st December 2017 06:06
    • Replies: 5
    • Views: 829
    2nd December 2017, 13:07 Go to last post
  25. SPI communication (ALTERA board)

    Started by MiLaNa1995, 30th November 2017 14:19
    • Replies: 1
    • Views: 387
    2nd December 2017, 09:36 Go to last post