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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 18,109
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 25,005
    21st March 2007, 21:21 Go to last post
  1. Reading numbers and assign them to an array

    Started by mahmood.n, 23rd June 2017 10:48
    • Replies: 13
    • Views: 649
    Today, 18:55 Go to last post
  2. Real life throughput of FPGA DSP blocks

    Started by shaiko, Yesterday 15:15
    • Replies: 7
    • Views: 369
    Today, 08:40 Go to last post
    • Replies: 6
    • Views: 528
    22nd June 2017, 11:28 Go to last post
    • Replies: 1
    • Views: 128
    22nd June 2017, 11:24 Go to last post
    • Replies: 3
    • Views: 196
    22nd June 2017, 10:03 Go to last post
    • Replies: 2
    • Views: 186
    22nd June 2017, 06:29 Go to last post
  3. 4 to 11 Decoder in VerilogA

    Started by PaulineVi, 21st June 2017 14:59
    • Replies: 6
    • Views: 315
    21st June 2017, 18:58 Go to last post
  4. matrix array from instantiations

    Started by nizdom, 21st June 2017 10:33
    • Replies: 1
    • Views: 194
    21st June 2017, 16:07 Go to last post
  5. VHDL Comparison Tree

    Started by shaiko, 18th June 2017 17:48
    • Replies: 18
    • Views: 1,096
    21st June 2017, 07:56 Go to last post
  6. USB blaster fail to work after Quartus update

    Started by mahmood.n, 20th June 2017 16:48
    • Replies: 3
    • Views: 375
    20th June 2017, 23:56 Go to last post
  7. Atmel/Microchip ATF750 series programmer???

    Started by whack, 20th June 2017 15:50
    • Replies: 0
    • Views: 155
    20th June 2017, 15:50 Go to last post
    • Replies: 1
    • Views: 200
    20th June 2017, 14:46 Go to last post
  8. send/receive data to/from fpga device

    Started by mahmood.n, 16th June 2017 09:24
    • Replies: 11
    • Views: 902
    17th June 2017, 09:32 Go to last post
  9. How to avoid using clock trees in Zynq FPGAs?

    Started by msdarvishi, 15th June 2017 00:35
    • Replies: 4
    • Views: 437
    17th June 2017, 00:47 Go to last post
    • Replies: 4
    • Views: 285
    17th June 2017, 00:42 Go to last post
  10. Single multiplier takes up a whole DSP block for

    Started by shaiko, 14th June 2017 15:51
    • Replies: 13
    • Views: 759
    16th June 2017, 08:54 Go to last post
  11. Quartus not show the port size correctly

    Started by mahmood.n, 15th June 2017 23:12
    • Replies: 2
    • Views: 396
    16th June 2017, 07:43 Go to last post
  12. simulation-based faults injection

    Started by ouij, 12th June 2017 11:23
    • Replies: 7
    • Views: 541
    15th June 2017, 15:41 Go to last post
  13. binary dividing: restoring method

    Started by kk_0, 13th June 2017 20:32
    • Replies: 3
    • Views: 436
    14th June 2017, 22:22 Go to last post
    • Replies: 3
    • Views: 670
    14th June 2017, 18:01 Go to last post
  14. PWM for LED module to choose duty cycle

    Started by manush30, 28th May 2017 14:22
    • Replies: 6
    • Views: 798
    14th June 2017, 17:34 Go to last post
  15. Synthesis: Check_Design Report too many warnings

    Started by Johannah, 13th June 2017 08:48
    • Replies: 3
    • Views: 249
    14th June 2017, 15:41 Go to last post
  16. Register vs BRAM vs slice count

    Started by Tarunfpga1, 13th June 2017 08:58
    • Replies: 1
    • Views: 288
    13th June 2017, 19:04 Go to last post
  17. How to work out with "inout" port in verilog?

    Started by hcu, 13th June 2017 06:41
    • Replies: 8
    • Views: 446
    13th June 2017, 18:46 Go to last post
  18. Temperature and Voltage Monitoring using XADC

    Started by beginner_EDA, 13th June 2017 14:29
    • Replies: 1
    • Views: 225
    13th June 2017, 16:16 Go to last post
    • Replies: 4
    • Views: 634
    13th June 2017, 16:13 Go to last post
  19. A pseudo-random number generator

    Started by Binome, 13th June 2017 10:25
    • Replies: 4
    • Views: 235
    13th June 2017, 14:15 Go to last post
  20. WARNING:NgdBuild:486 in xilinx

    Started by ecasha, 13th June 2017 04:25
    • Replies: 1
    • Views: 275
    13th June 2017, 08:46 Go to last post
  21. [SOLVED] FPGA: Different behavior after synthesis

    Started by birbal, 12th June 2017 22:23
    • Replies: 4
    • Views: 402
    12th June 2017, 23:42 Go to last post