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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 17,389
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 24,497
    21st March 2007, 21:21 Go to last post
  1. Timing Constraints for external clocks

    Started by incisive29, Yesterday 11:16
    • Replies: 3
    • Views: 170
    Yesterday, 18:03 Go to last post
    • Replies: 13
    • Views: 741
    Yesterday, 12:40 Go to last post
  2. [moved] CLKBUF and INBUF actel FPGA

    Started by incisive29, Yesterday 11:01
    • Replies: 0
    • Views: 34
    Yesterday, 11:01 Go to last post
  3. [MOVED]Fetching Pdb file from Actel FPGA

    Started by incisive29, Yesterday 10:56
    • Replies: 0
    • Views: 62
    Yesterday, 10:56 Go to last post
  4. Need Help regarding Actel FPGA Area Constraints

    Started by saad_sipra, 10th May 2017 16:06
    • Replies: 15
    • Views: 1,288
    Yesterday, 10:36 Go to last post
  5. Crystal Oscillators instead of FPGA Clock

    Started by Kibos, 26th May 2017 13:41
    • Replies: 7
    • Views: 682
    27th May 2017, 09:41 Go to last post
  6. Reading a block RAM Xilinx IP Core

    Started by beginner_EDA, 26th May 2017 13:04
    • Replies: 3
    • Views: 170
    26th May 2017, 16:11 Go to last post
  7. creating axi slave peripheral in vivado ?

    Started by hcu, 25th May 2017 16:58
    • Replies: 3
    • Views: 153
    25th May 2017, 19:10 Go to last post
    • Replies: 7
    • Views: 265
    24th May 2017, 16:57 Go to last post
    • Replies: 10
    • Views: 641
    24th May 2017, 08:38 Go to last post
  8. SPI sample code using FPGA

    Started by myjoe1026, 22nd May 2017 07:14
    • Replies: 13
    • Views: 589
    24th May 2017, 04:02 Go to last post
    • Replies: 10
    • Views: 621
    23rd May 2017, 12:44 Go to last post
  9. FPGA or CPLD with hadware serial number?

    Started by hardware_guy, 21st May 2017 15:36
    • Replies: 4
    • Views: 311
    23rd May 2017, 00:24 Go to last post
  10. i2c vhdl example code

    Started by amir_rch, 20th May 2017 13:14
    • Replies: 4
    • Views: 549
    22nd May 2017, 16:12 Go to last post
  11. B&R Automation Studio

    Started by sunshine2016, 12th May 2017 21:23
    • Replies: 3
    • Views: 300
    22nd May 2017, 16:09 Go to last post
  12. 128x64zw lcd interfacing with fpga

    Started by zacief, 16th May 2017 12:43
    • Replies: 10
    • Views: 597
    21st May 2017, 13:39 Go to last post
  13. Unable to infer RAM on Quartus Prime

    Started by FecP, 18th May 2017 17:00
    • Replies: 8
    • Views: 628
    20th May 2017, 09:29 Go to last post
  14. Working with a SPARTAN6 board

    Started by mahmood.n, 18th May 2017 12:26
    • Replies: 13
    • Views: 539
    20th May 2017, 08:24 Go to last post
  15. verilog code for addition of contents in the memory

    Started by ecasha, 17th May 2017 18:35
    • Replies: 8
    • Views: 541
    19th May 2017, 06:46 Go to last post
  16. RPN Calculator using VHDL

    Started by NightOWL, 18th May 2017 20:30
    • Replies: 1
    • Views: 312
    19th May 2017, 00:23 Go to last post
  17. VHDL Design Problem Issues

    Started by dzafar, 15th May 2017 10:20
    • Replies: 14
    • Views: 663
    17th May 2017, 23:22 Go to last post
  18. 2 way communication between modules in VHDL

    Started by nizdom, 16th May 2017 15:10
    • Replies: 6
    • Views: 432
    17th May 2017, 16:26 Go to last post
  19. how to create matrix in VHDL

    Started by nizdom, 15th May 2017 15:46
    • Replies: 10
    • Views: 410
    17th May 2017, 13:13 Go to last post
    • Replies: 2
    • Views: 340
    17th May 2017, 06:03 Go to last post
  20. FPGA WARNING of initial value is never assigned

    Started by myjoe1026, 15th May 2017 10:39
    • Replies: 15
    • Views: 567
    17th May 2017, 04:38 Go to last post
    • Replies: 3
    • Views: 258
    17th May 2017, 03:54 Go to last post