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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 24,353
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,155
    21st March 2007, 21:21 Go to last post
  1. VHDL state machine execution

    Started by hareeshP, 21st April 2018 12:15
    • Replies: 5
    • Views: 273
    Today, 06:58 Go to last post
  2. Artix 7 xc7a35t FPGA board

    Started by ananthan95, Yesterday 13:02
    • Replies: 4
    • Views: 82
    Today, 06:13 Go to last post
  3. Nonconstant index in Verilog

    Started by wittman, Today 04:24
    • Replies: 0
    • Views: 50
    Today, 04:24 Go to last post
  4. simulation problem vhdl

    Started by 7mod998, 23rd April 2018 20:35
    • Replies: 2
    • Views: 127
    Yesterday, 10:30 Go to last post
  5. testbench without a DUT

    Started by paulr127, 19th April 2018 22:20
    • Replies: 13
    • Views: 400
    23rd April 2018, 14:36 Go to last post
  6. I have issues using a delay in VHDL

    Started by ggiacomo, 22nd April 2018 12:23
    • Replies: 3
    • Views: 174
    23rd April 2018, 09:37 Go to last post
  7. NI MyRIO with VHDL codes

    Started by pattern, 23rd April 2018 09:20
    • Replies: 0
    • Views: 57
    23rd April 2018, 09:20 Go to last post
  8. synplify identify instrumentor......

    Started by velu.plg, 21st April 2018 09:57
    • Replies: 1
    • Views: 126
    21st April 2018, 16:19 Go to last post
  9. [SOLVED] Glitch Filter VHDL // Lattice document

    Started by player80, 20th April 2018 14:43
    • Replies: 6
    • Views: 256
    20th April 2018, 20:08 Go to last post
  10. Help with this FPGA xilinx spartan xc3s50

    Started by FGDGDFGG, 18th April 2018 10:46
    • Replies: 5
    • Views: 346
    20th April 2018, 15:41 Go to last post
    • Replies: 5
    • Views: 218
    20th April 2018, 09:39 Go to last post
  11. [SOLVED] How do I read a test bench input from a txt file?

    Started by ggiacomo, 17th April 2018 09:55
    • Replies: 6
    • Views: 240
    19th April 2018, 18:39 Go to last post
  12. best method for control memory in fpga

    Started by jalal.baba, 17th April 2018 19:51
    • Replies: 5
    • Views: 260
    19th April 2018, 08:55 Go to last post
  13. altera fpga update from remote

    Started by franticEB, 18th April 2018 17:45
    • Replies: 1
    • Views: 162
    18th April 2018, 22:28 Go to last post
    • Replies: 0
    • Views: 113
    18th April 2018, 14:19 Go to last post
    • Replies: 7
    • Views: 483
    15th April 2018, 07:42 Go to last post
  14. Cannot continue(fatal error) problems with lifo

    Started by chenobi, 13th April 2018 12:11
    • Replies: 8
    • Views: 385
    13th April 2018, 17:46 Go to last post
    • Replies: 6
    • Views: 506
    13th April 2018, 12:40 Go to last post
  15. if statement within a generate for loop

    Started by jasmine123, 12th April 2018 07:47
    • Replies: 7
    • Views: 359
    13th April 2018, 03:19 Go to last post
  16. setup violation in physical designing

    Started by vinu114, 12th April 2018 07:05
    • Replies: 3
    • Views: 256
    13th April 2018, 01:44 Go to last post
    • Replies: 8
    • Views: 657
    12th April 2018, 10:00 Go to last post
  17. Timing constraints for clock domain crossing

    Started by urbanzrim, 10th April 2018 07:31
    • Replies: 6
    • Views: 420
    12th April 2018, 05:45 Go to last post
  18. Is logic cell a technology independent parameter

    Started by rafimiet, 11th April 2018 09:58
    • Replies: 7
    • Views: 388
    12th April 2018, 04:51 Go to last post
  19. Simulating Xilinx smpte sdi core

    Started by paulr127, 10th April 2018 12:04
    • Replies: 8
    • Views: 450
    11th April 2018, 15:12 Go to last post
  20. Kintex Transceiver bank configuration

    Started by beginner_EDA, 11th April 2018 13:39
    • Replies: 0
    • Views: 228
    11th April 2018, 13:39 Go to last post
  21. Output pixel larger than the desired pixel

    Started by fatimamaz, 27th March 2018 13:04
    • Replies: 3
    • Views: 512
    10th April 2018, 10:21 Go to last post
  22. [SOLVED] Verilog error , Pls help

    Started by abimann, 16th March 2018 16:31
    • Replies: 13
    • Views: 1,225
    10th April 2018, 02:29 Go to last post
  23. Assignment of DSP Slices in FPGA

    Started by expertengr, 6th April 2018 10:07
    • Replies: 5
    • Views: 432
    9th April 2018, 18:47 Go to last post