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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 20,477
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 26,720
    21st March 2007, 21:21 Go to last post
  1. Logic scope coding approach

    Started by promach, 16th September 2017 10:15
    2 Pages
    1 2
    • Replies: 22
    • Views: 539
    Today, 04:04 Go to last post
    • Replies: 6
    • Views: 313
    Today, 00:48 Go to last post
  2. Frame buffer controller with dual_clock FIFO

    Started by Taki_comp, 19th September 2017 18:22
    • Replies: 6
    • Views: 159
    Yesterday, 04:40 Go to last post
    • Replies: 2
    • Views: 146
    19th September 2017, 10:28 Go to last post
  3. Is that considered a combinatorial loop and how bad is it ?

    Started by joul, 16th September 2017 16:01
    • Replies: 8
    • Views: 285
    18th September 2017, 10:16 Go to last post
  4. How to Declare a 3D array as an input inside the port

    Started by Yogeshwaran, 16th September 2017 12:15
    • Replies: 4
    • Views: 204
    17th September 2017, 15:54 Go to last post
  5. I2C delay between SCL and SDA

    Started by manush30, 14th September 2017 15:44
    • Replies: 3
    • Views: 219
    17th September 2017, 15:43 Go to last post
  6. Reading ufm of max ii

    Started by hareeshP, 14th September 2017 14:41
    • Replies: 10
    • Views: 341
    17th September 2017, 09:27 Go to last post
    • Replies: 3
    • Views: 244
    16th September 2017, 19:04 Go to last post
  7. need some help to design digital circuit

    Started by Adnan86, 15th September 2017 19:08
    • Replies: 12
    • Views: 357
    16th September 2017, 15:55 Go to last post
    • Replies: 3
    • Views: 306
    15th September 2017, 19:18 Go to last post
  8. Timestamp implementation in FPGA

    Started by beginner_EDA, 15th September 2017 11:13
    • Replies: 2
    • Views: 174
    15th September 2017, 14:26 Go to last post
  9. Monitoring different clock domains in chipscope pro

    Started by Taki_comp, 14th September 2017 13:22
    • Replies: 3
    • Views: 164
    14th September 2017, 19:35 Go to last post
  10. Timing simulations in vivado

    Started by rafimiet, 14th September 2017 13:58
    • Replies: 4
    • Views: 148
    14th September 2017, 17:56 Go to last post
  11. [SOLVED] "ERROR: [Common 17-165] Too many positional options when parsing

    Started by rafimiet, 13th September 2017 07:55
    • Replies: 7
    • Views: 264
    14th September 2017, 10:51 Go to last post
  12. Throughput calculation on design in XIlinx

    Started by ramdin2006, 13th September 2017 04:39
    • Replies: 3
    • Views: 217
    14th September 2017, 10:17 Go to last post
  13. [SOLVED] adc daughter card unsigned output

    Started by dipin, 12th September 2017 13:19
    • Replies: 5
    • Views: 235
    13th September 2017, 09:56 Go to last post
  14. Initializing a very long vector with some repetition

    Started by rafimiet, 12th September 2017 12:59
    • Replies: 8
    • Views: 233
    13th September 2017, 09:28 Go to last post
  15. Cyclone ii fpga flash memory erasing

    Started by hareeshP, 12th September 2017 09:33
    • Replies: 8
    • Views: 281
    13th September 2017, 06:03 Go to last post
  16. word's length of single port RAM

    Started by tanish, 12th September 2017 14:24
    • Replies: 5
    • Views: 221
    13th September 2017, 00:28 Go to last post
    • Replies: 7
    • Views: 191
    12th September 2017, 10:44 Go to last post
  17. Solving hold time problems via SDC only

    Started by shaiko, 10th September 2017 12:04
    • Replies: 8
    • Views: 431
    12th September 2017, 09:12 Go to last post
    • Replies: 6
    • Views: 365
    12th September 2017, 05:20 Go to last post
  18. Using a buffer to modify an input port

    Started by mahmood.n, 11th September 2017 15:54
    • Replies: 11
    • Views: 269
    11th September 2017, 22:05 Go to last post
  19. [SOLVED] ERROR:HDLParsers:3375

    Started by rafimiet, 11th September 2017 18:04
    • Replies: 1
    • Views: 161
    11th September 2017, 18:57 Go to last post
  20. Better performance measure LUT vs FF

    Started by SharpWeapon, 9th September 2017 14:30
    • Replies: 6
    • Views: 288
    11th September 2017, 18:08 Go to last post
  21. Accessing range of array elements VHDL

    Started by Curios_Eng, 11th September 2017 11:53
    • Replies: 2
    • Views: 179
    11th September 2017, 16:46 Go to last post
  22. simulation in vivado vs ISIM(in Xilinx ISE)

    Started by rafimiet, 10th September 2017 05:30
    • Replies: 3
    • Views: 294
    11th September 2017, 13:12 Go to last post
  23. Run all Vivado synthesis strategies in one run

    Started by SharpWeapon, 9th September 2017 14:25
    • Replies: 1
    • Views: 209
    11th September 2017, 09:24 Go to last post
  24. Avalon BFM burst operation.

    Started by muthu7495, 11th September 2017 08:07
    • Replies: 0
    • Views: 206
    11th September 2017, 08:07 Go to last post