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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 18,736
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 25,455
    21st March 2007, 21:21 Go to last post
  1. Making GPIO pin of FPGA high.

    Started by hareeshP, Yesterday 14:38
    • Replies: 7
    • Views: 284
    Today, 10:02 Go to last post
  2. Basic questions regarding NIOS

    Started by mahmood.n, Yesterday 10:16
    • Replies: 3
    • Views: 131
    Yesterday, 13:22 Go to last post
  3. VHDL Register transferring.

    Started by hareeshP, 19th July 2017 13:28
    • Replies: 5
    • Views: 365
    19th July 2017, 15:16 Go to last post
    • Replies: 3
    • Views: 212
    19th July 2017, 14:39 Go to last post
  4. VHDL Constant Declaration

    Started by hareeshP, 19th July 2017 05:16
    • Replies: 13
    • Views: 289
    19th July 2017, 14:09 Go to last post
    • Replies: 5
    • Views: 280
    19th July 2017, 05:04 Go to last post
    • Replies: 3
    • Views: 343
    18th July 2017, 19:00 Go to last post
  5. Multicast address in 10 Gig Ethernet IP

    Started by beginner_EDA, 18th July 2017 14:00
    • Replies: 3
    • Views: 156
    18th July 2017, 15:06 Go to last post
  6. how to use spi interface with custom ip

    Started by abhishek7, 18th July 2017 09:43
    • Replies: 1
    • Views: 177
    18th July 2017, 10:46 Go to last post
  7. VHDL array comparison

    Started by Telboy99, 16th July 2017 12:35
    • Replies: 3
    • Views: 350
    17th July 2017, 13:31 Go to last post
  8. Programmable Priority Encoder

    Started by RatedR, 13th July 2017 17:00
    • Replies: 7
    • Views: 570
    17th July 2017, 00:51 Go to last post
  9. ADC with Qsys tool Altera

    Started by grezzoman, 3rd July 2017 15:30
    • Replies: 2
    • Views: 322
    16th July 2017, 23:53 Go to last post
  10. use C to program FPGA

    Started by matin-kh, 2nd July 2017 12:39
    • Replies: 9
    • Views: 991
    16th July 2017, 23:43 Go to last post
  11. Monolithic vs non-Monolithic FPGA

    Started by shaiko, 14th July 2017 13:58
    • Replies: 7
    • Views: 346
    15th July 2017, 00:06 Go to last post
    • Replies: 1
    • Views: 239
    14th July 2017, 07:06 Go to last post
  12. TimeQuest analysis for pulse width

    Started by mahmood.n, 13th July 2017 11:18
    • Replies: 1
    • Views: 413
    13th July 2017, 19:11 Go to last post
  13. question about CMT of the spartan 6

    Started by matin-kh, 12th July 2017 12:20
    • Replies: 1
    • Views: 364
    13th July 2017, 02:24 Go to last post
  14. What FPGA logic do constants consume

    Started by shaiko, 11th July 2017 22:20
    • Replies: 7
    • Views: 662
    12th July 2017, 17:13 Go to last post
  15. Strange simulator behavior for code in Verilog

    Started by Gizmotoy, 10th July 2017 23:34
    • Replies: 9
    • Views: 561
    11th July 2017, 22:21 Go to last post
    • Replies: 14
    • Views: 866
    11th July 2017, 17:56 Go to last post
  16. Implementing Look up table in FPGA

    Started by beginner_EDA, 5th July 2017 15:55
    • Replies: 13
    • Views: 732
    11th July 2017, 13:51 Go to last post
  17. Synthesis: Check_Design Report too many warnings

    Started by Johannah, 13th June 2017 08:48
    • Replies: 6
    • Views: 774
    11th July 2017, 08:40 Go to last post
    • Replies: 2
    • Views: 262
    10th July 2017, 18:21 Go to last post
  18. signal value conflict in VHDL

    Started by mahmood.n, 9th July 2017 12:03
    • Replies: 16
    • Views: 787
    10th July 2017, 16:49 Go to last post
  19. Difference b/w asynchronous Vs synchronous FIFO

    Started by rac70, 7th July 2017 12:53
    • Replies: 5
    • Views: 378
    10th July 2017, 10:39 Go to last post
  20. getting and passing data in CPLD

    Started by linam, 7th July 2017 09:38
    • Replies: 3
    • Views: 546
    9th July 2017, 10:36 Go to last post