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Threads 1 to 30 of 21685

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 18,173
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 25,052
    21st March 2007, 21:21 Go to last post
  1. bitwise function description

    Started by Binome, Yesterday 16:22
    • Replies: 1
    • Views: 233
    Yesterday, 17:23 Go to last post
  2. [SOLVED] How to have an undefined range in function?

    Started by wesleytaylor, 26th June 2017 13:49
    • Replies: 3
    • Views: 255
    Yesterday, 10:09 Go to last post
    • Replies: 5
    • Views: 464
    Yesterday, 06:02 Go to last post
  3. Real life throughput of FPGA DSP blocks

    Started by shaiko, 24th June 2017 15:15
    • Replies: 10
    • Views: 527
    Yesterday, 04:56 Go to last post
  4. First Design with Quartus Prime

    Started by zionico90, 26th June 2017 14:54
    • Replies: 1
    • Views: 100
    26th June 2017, 15:18 Go to last post
    • Replies: 3
    • Views: 313
    26th June 2017, 11:42 Go to last post
  5. Reading numbers and assign them to an array

    Started by mahmood.n, 23rd June 2017 10:48
    • Replies: 13
    • Views: 842
    25th June 2017, 18:55 Go to last post
    • Replies: 6
    • Views: 559
    22nd June 2017, 11:28 Go to last post
    • Replies: 1
    • Views: 153
    22nd June 2017, 11:24 Go to last post
    • Replies: 3
    • Views: 227
    22nd June 2017, 10:03 Go to last post
    • Replies: 2
    • Views: 213
    22nd June 2017, 06:29 Go to last post
  6. 4 to 11 Decoder in VerilogA

    Started by PaulineVi, 21st June 2017 14:59
    • Replies: 6
    • Views: 339
    21st June 2017, 18:58 Go to last post
  7. matrix array from instantiations

    Started by nizdom, 21st June 2017 10:33
    • Replies: 1
    • Views: 219
    21st June 2017, 16:07 Go to last post
  8. VHDL Comparison Tree

    Started by shaiko, 18th June 2017 17:48
    • Replies: 18
    • Views: 1,141
    21st June 2017, 07:56 Go to last post
  9. USB blaster fail to work after Quartus update

    Started by mahmood.n, 20th June 2017 16:48
    • Replies: 3
    • Views: 402
    20th June 2017, 23:56 Go to last post
  10. Atmel/Microchip ATF750 series programmer???

    Started by whack, 20th June 2017 15:50
    • Replies: 0
    • Views: 181
    20th June 2017, 15:50 Go to last post
    • Replies: 1
    • Views: 224
    20th June 2017, 14:46 Go to last post
  11. send/receive data to/from fpga device

    Started by mahmood.n, 16th June 2017 09:24
    • Replies: 11
    • Views: 931
    17th June 2017, 09:32 Go to last post
  12. How to avoid using clock trees in Zynq FPGAs?

    Started by msdarvishi, 15th June 2017 00:35
    • Replies: 4
    • Views: 469
    17th June 2017, 00:47 Go to last post
    • Replies: 4
    • Views: 313
    17th June 2017, 00:42 Go to last post
  13. Single multiplier takes up a whole DSP block for

    Started by shaiko, 14th June 2017 15:51
    • Replies: 13
    • Views: 789
    16th June 2017, 08:54 Go to last post
  14. Quartus not show the port size correctly

    Started by mahmood.n, 15th June 2017 23:12
    • Replies: 2
    • Views: 422
    16th June 2017, 07:43 Go to last post
  15. simulation-based faults injection

    Started by ouij, 12th June 2017 11:23
    • Replies: 7
    • Views: 570
    15th June 2017, 15:41 Go to last post
  16. binary dividing: restoring method

    Started by kk_0, 13th June 2017 20:32
    • Replies: 3
    • Views: 459
    14th June 2017, 22:22 Go to last post
    • Replies: 3
    • Views: 698
    14th June 2017, 18:01 Go to last post
  17. PWM for LED module to choose duty cycle

    Started by manush30, 28th May 2017 14:22
    • Replies: 6
    • Views: 825
    14th June 2017, 17:34 Go to last post
  18. Synthesis: Check_Design Report too many warnings

    Started by Johannah, 13th June 2017 08:48
    • Replies: 3
    • Views: 271
    14th June 2017, 15:41 Go to last post
  19. Register vs BRAM vs slice count

    Started by Tarunfpga1, 13th June 2017 08:58
    • Replies: 1
    • Views: 311
    13th June 2017, 19:04 Go to last post
  20. How to work out with "inout" port in verilog?

    Started by hcu, 13th June 2017 06:41
    • Replies: 8
    • Views: 471
    13th June 2017, 18:46 Go to last post
  21. Temperature and Voltage Monitoring using XADC

    Started by beginner_EDA, 13th June 2017 14:29
    • Replies: 1
    • Views: 247
    13th June 2017, 16:16 Go to last post