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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 23,303
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 29,103
    21st March 2007, 21:21 Go to last post
  1. I/O pin FPGA voltage level translation for interfacing

    Started by fpga93, 19th January 2018 09:35
    • Replies: 7
    • Views: 376
    Yesterday, 21:36 Go to last post
    • Replies: 0
    • Views: 89
    Yesterday, 14:17 Go to last post
  2. Clock generator in psoc by using verilog

    Started by jasi, Yesterday 10:29
    • Replies: 1
    • Views: 81
    Yesterday, 11:01 Go to last post
  3. [SOLVED] [Verilog] Clock enable causes glitch on ouptut - Best resolution

    Started by pigtwo, 20th January 2018 23:07
    • Replies: 5
    • Views: 374
    22nd January 2018, 17:40 Go to last post
    • Replies: 2
    • Views: 190
    22nd January 2018, 17:04 Go to last post
  4. MAX 10 pin assignment error

    Started by hareeshP, 22nd January 2018 13:00
    • Replies: 0
    • Views: 116
    22nd January 2018, 13:00 Go to last post
  5. [old software] XC3000/A Software

    Started by DeepTHought, 20th January 2018 16:45
    • Replies: 1
    • Views: 184
    21st January 2018, 03:34 Go to last post
    • Replies: 0
    • Views: 113
    20th January 2018, 22:43 Go to last post
  6. CY7C68013A labview interface

    Started by jackobian, 12th January 2018 11:04
    • Replies: 1
    • Views: 306
    20th January 2018, 16:55 Go to last post
  7. non responsive vhdl code in FPGA board

    Started by ananthan95, 29th December 2017 06:58
    • Replies: 10
    • Views: 773
    19th January 2018, 09:13 Go to last post
  8. [SOLVED] Integer convert to std_logic_vector ?

    Started by abimann, 30th December 2017 17:33
    • Replies: 3
    • Views: 476
    19th January 2018, 08:48 Go to last post
  9. Error in verilog code for stopwatch

    Started by Nyom, 18th January 2018 22:59
    • Replies: 6
    • Views: 285
    19th January 2018, 01:30 Go to last post
    • Replies: 5
    • Views: 428
    18th January 2018, 14:19 Go to last post
    • Replies: 4
    • Views: 439
    18th January 2018, 10:52 Go to last post
  10. TIBPAL22vp10 compiler

    Started by wjr1955, 17th January 2018 21:28
    • Replies: 1
    • Views: 187
    18th January 2018, 10:05 Go to last post
  11. [SOLVED] How to receive PWM and edit it ?

    Started by abimann, 30th December 2017 17:39
    • Replies: 13
    • Views: 945
    16th January 2018, 08:08 Go to last post
  12. Conversion from std_logic_vector to sfixed

    Started by Hugo17, 15th January 2018 08:31
    • Replies: 2
    • Views: 236
    16th January 2018, 07:06 Go to last post
  13. Wait on clocking block input signals

    Started by amvrao, 12th January 2018 12:48
    • Replies: 2
    • Views: 390
    15th January 2018, 15:59 Go to last post
    • Replies: 4
    • Views: 401
    15th January 2018, 09:27 Go to last post
    • Replies: 4
    • Views: 268
    12th January 2018, 14:32 Go to last post
    • Replies: 4
    • Views: 318
    12th January 2018, 07:29 Go to last post
    • Replies: 4
    • Views: 456
    10th January 2018, 20:30 Go to last post
    • Replies: 0
    • Views: 217
    10th January 2018, 14:20 Go to last post
    • Replies: 7
    • Views: 431
    10th January 2018, 12:35 Go to last post
  14. [SOLVED] irrational clk period

    Started by nsgil85, 31st December 2017 08:59
    2 Pages
    1 2
    • Replies: 26
    • Views: 1,191
    8th January 2018, 17:00 Go to last post
  15. QPSK Modulator Design Issues

    Started by NichollsGlen, 28th December 2017 03:39
    • Replies: 2
    • Views: 487
    8th January 2018, 02:44 Go to last post
  16. [Altera] altera_mf lib -> how to compile/map?

    Started by ivlsi, 7th January 2018 02:53
    • Replies: 0
    • Views: 313
    7th January 2018, 02:53 Go to last post