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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 22,683
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 28,458
    21st March 2007, 21:21 Go to last post
  1. Generate desired random number in range in verilog

    Started by tayyab786, 27th November 2017 20:14
    • Replies: 14
    • Views: 1,285
    Yesterday, 22:26 Go to last post
    • Replies: 5
    • Views: 154
    Yesterday, 22:10 Go to last post
  2. Moved: range of lfsr depend upon input value

    Started by tayyab786, Yesterday 22:17
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  3. rount-robin arbiter with ring counter.

    Started by ppko1233, Yesterday 14:26
    • Replies: 0
    • Views: 61
    Yesterday, 14:26 Go to last post
  4. Improve UART resource usage

    Started by promach, Yesterday 12:41
    • Replies: 0
    • Views: 96
    Yesterday, 12:41 Go to last post
  5. FPGA USB Data software

    Started by expertengr, 9th December 2017 12:10
    • Replies: 4
    • Views: 202
    Yesterday, 11:06 Go to last post
  6. Circuit protection with VHDL code

    Started by manush30, 6th December 2017 08:40
    • Replies: 9
    • Views: 459
    Yesterday, 10:54 Go to last post
    • Replies: 0
    • Views: 211
    Yesterday, 00:00 Go to last post
    • Replies: 2
    • Views: 154
    9th December 2017, 20:11 Go to last post
    • Replies: 4
    • Views: 586
    9th December 2017, 16:34 Go to last post
  7. Altera Stratix 10 Hyper-Registers

    Started by Wiljan, 9th December 2017 14:24
    • Replies: 0
    • Views: 125
    9th December 2017, 14:24 Go to last post
  8. choosing high speed data storage element

    Started by amin5659, 7th December 2017 16:42
    • Replies: 10
    • Views: 461
    9th December 2017, 10:39 Go to last post
  9. How to load program to A54SX16A-PQG208M FPGA?

    Started by Mithun_K_Das, 5th December 2017 12:17
    • Replies: 13
    • Views: 836
    9th December 2017, 05:34 Go to last post
    • Replies: 4
    • Views: 253
    8th December 2017, 22:19 Go to last post
  10. How to run two module in series using verilog

    Started by kapaa, 7th December 2017 03:21
    • Replies: 6
    • Views: 426
    7th December 2017, 22:44 Go to last post
  11. FPGA-Based Christmas project

    Started by bwarlord01, 6th December 2017 19:29
    • Replies: 3
    • Views: 354
    7th December 2017, 02:46 Go to last post
  12. What is Most Economic FPGA?

    Started by Zerox100, 5th December 2017 16:04
    • Replies: 2
    • Views: 304
    6th December 2017, 12:59 Go to last post
    • Replies: 0
    • Views: 168
    6th December 2017, 12:18 Go to last post
  13. Vendor specific macros for Igloo2

    Started by filip.amator, 5th December 2017 23:15
    • Replies: 2
    • Views: 418
    6th December 2017, 11:38 Go to last post
  14. ppg database regarding

    Started by josephine1234, 5th December 2017 12:00
    • Replies: 1
    • Views: 163
    5th December 2017, 12:13 Go to last post
  15. Simulation time in simulation tools like ISIM/model sim

    Started by mjuneja, 5th December 2017 08:25
    • Replies: 3
    • Views: 287
    5th December 2017, 10:56 Go to last post
  16. FPGA Ethernet interface

    Started by Vlad., 3rd December 2017 19:11
    • Replies: 3
    • Views: 1,035
    4th December 2017, 09:51 Go to last post
  17. Vivado HLS Experience

    Started by MarkPh, 1st December 2017 15:58
    • Replies: 2
    • Views: 499
    3rd December 2017, 07:48 Go to last post
  18. Regarding Verilog codes

    Started by josephine1234, 1st December 2017 06:06
    • Replies: 5
    • Views: 782
    2nd December 2017, 13:07 Go to last post
  19. SPI communication (ALTERA board)

    Started by MiLaNa1995, 30th November 2017 14:19
    • Replies: 1
    • Views: 344
    2nd December 2017, 09:36 Go to last post
  20. Multiple users of a DDR interface

    Started by shaiko, 29th November 2017 21:08
    • Replies: 14
    • Views: 1,081
    2nd December 2017, 09:31 Go to last post
  21. Coding help in Verilog

    Started by josephine1234, 1st December 2017 06:04
    • Replies: 4
    • Views: 428
    1st December 2017, 13:18 Go to last post
  22. Implementation of output wrt clock in verilog

    Started by kapaa, 30th November 2017 08:24
    • Replies: 5
    • Views: 529
    1st December 2017, 07:01 Go to last post
  23. Interfacing a VGA port with a PLD

    Started by garvind25, 25th October 2017 07:16
    • Replies: 10
    • Views: 1,016
    1st December 2017, 06:10 Go to last post
  24. modelsim error during RTL simulation

    Started by hareeshP, 30th November 2017 15:07
    • Replies: 8
    • Views: 480
    30th November 2017, 19:33 Go to last post