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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 21,256
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 27,298
    21st March 2007, 21:21 Go to last post
  1. Problem facing in Xpower Analyzer

    Started by qaziarbab, 12th October 2017 16:01
    • Replies: 6
    • Views: 266
    Yesterday, 19:07 Go to last post
    • Replies: 18
    • Views: 721
    Yesterday, 18:35 Go to last post
    • Replies: 0
    • Views: 117
    Yesterday, 06:04 Go to last post
  2. Programmable Priority Encoder

    Started by RatedR, 13th July 2017 17:00
    • Replies: 13
    • Views: 1,757
    17th October 2017, 17:47 Go to last post
  3. generate vhdl netlist by ise

    Started by moonshine8995, 14th October 2017 17:42
    • Replies: 4
    • Views: 352
    16th October 2017, 09:47 Go to last post
  4. Intialization of SDRAM DDR2 memory in Xilinx tools

    Started by Taki_comp, 13th October 2017 12:12
    • Replies: 6
    • Views: 350
    15th October 2017, 16:01 Go to last post
  5. Verilog Syntax error

    Started by hansben, 14th October 2017 05:16
    • Replies: 1
    • Views: 267
    14th October 2017, 07:43 Go to last post
    • Replies: 2
    • Views: 163
    12th October 2017, 14:13 Go to last post
    • Replies: 1
    • Views: 278
    12th October 2017, 02:30 Go to last post
  6. Inequality operator in VHDL

    Started by nizdom, 11th October 2017 10:56
    • Replies: 2
    • Views: 205
    11th October 2017, 11:31 Go to last post
    • Replies: 4
    • Views: 311
    11th October 2017, 07:31 Go to last post
  7. Regarding connections in a CPLD schematic

    Started by garvind25, 10th October 2017 12:19
    • Replies: 6
    • Views: 280
    11th October 2017, 06:51 Go to last post
  8. Xilinx ISim - Post place and route simulation

    Started by NikosTS, 10th October 2017 16:08
    • Replies: 17
    • Views: 609
    11th October 2017, 00:32 Go to last post
    • Replies: 9
    • Views: 572
    10th October 2017, 16:32 Go to last post
  9. Trigger Signal in VHDL

    Started by nizdom, 9th October 2017 15:25
    • Replies: 6
    • Views: 284
    10th October 2017, 13:52 Go to last post
  10. dynamic array in verilog

    Started by tayyab786, 8th October 2017 09:16
    • Replies: 5
    • Views: 498
    10th October 2017, 12:32 Go to last post
  11. Help programming some Xilinx XC7236s

    Started by RobMUK, 9th October 2017 08:03
    • Replies: 2
    • Views: 252
    10th October 2017, 07:02 Go to last post
  12. does Synopsys Certify support customer design boards?

    Started by lcf0451, 10th October 2017 03:21
    • Replies: 0
    • Views: 247
    10th October 2017, 03:21 Go to last post
  13. vhdl codes for adpll-plz help

    Started by manishpatkar, 8th October 2017 17:20
    • Replies: 3
    • Views: 361
    9th October 2017, 15:58 Go to last post
  14. Vhdl when else statement error

    Started by hareeshP, 9th October 2017 10:22
    • Replies: 4
    • Views: 200
    9th October 2017, 10:34 Go to last post
    • Replies: 0
    • Views: 233
    9th October 2017, 07:04 Go to last post
  15. Pipeline problem VHDL

    Started by nizdom, 6th October 2017 16:24
    • Replies: 7
    • Views: 483
    7th October 2017, 21:42 Go to last post
    • Replies: 2
    • Views: 376
    6th October 2017, 15:24 Go to last post
  16. [SOLVED] Altering some bits of a RAM location

    Started by rafimiet, 6th October 2017 06:53
    • Replies: 2
    • Views: 294
    6th October 2017, 08:10 Go to last post
  17. [SOLVED] clearing the contents of single port RAM

    Started by rafimiet, 4th October 2017 13:17
    • Replies: 13
    • Views: 509
    6th October 2017, 04:28 Go to last post
  18. [Synth 8-27] complex assignment not supported

    Started by rafimiet, 5th October 2017 10:41
    • Replies: 4
    • Views: 435
    6th October 2017, 04:23 Go to last post
    • Replies: 1
    • Views: 339
    4th October 2017, 14:05 Go to last post