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Threads 21811 to 21840 of 22001

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Power Consumption in no-configured FPGA?

    Started by maestor, 12th June 2003 14:23
    • Replies: 0
    • Views: 1,423
    12th June 2003, 14:23 Go to last post
  2. Closed: free IP cores - links collection

    Started by ME, 11th June 2003 11:40
    • Replies: 2
    • Views: 1,876
    12th June 2003, 09:01 Go to last post
  3. Closed: what is a good jedec editor?

    Started by leilarazavi2000, 12th June 2003 07:08
    • Replies: 0
    • Views: 1,573
    12th June 2003, 07:08 Go to last post
  4. Closed: How to set the low power mode of macrocells of XC95108 ..

    Started by kras, 10th June 2003 09:50
    • Replies: 1
    • Views: 1,060
    10th June 2003, 11:11 Go to last post
  5. Closed: Anyone has FFT written in VHDL?

    Started by E. Madanian, 10th June 2003 05:41
    • Replies: 1
    • Views: 1,795
    10th June 2003, 08:25 Go to last post
  6. [SOLVED]Closed: I am looking for ip for 8051

    Started by , 9th June 2003 06:15
    • Replies: 0
    • Views: 863
    9th June 2003, 06:15 Go to last post
  7. Closed: ABEL HDL to VHDL convert

    Started by elcielo, 2nd June 2003 06:13
    • Replies: 2
    • Views: 5,697
    8th June 2003, 22:58 Go to last post
  8. Closed: link to Testing and Diagnosis of Digital Systems lecture

    Started by rohit_tech, 7th June 2003 09:44
    • Replies: 0
    • Views: 1,143
    7th June 2003, 09:44 Go to last post
  9. Closed: A Reconfigurable FPGA-Based Readback Signal Generator For Ha

    Started by pms_int, 6th June 2003 04:42
    • Replies: 3
    • Views: 1,353
    6th June 2003, 04:48 Go to last post
  10. Closed: VoIP anyone knows that ???

    Started by snake, 23rd May 2003 21:57
    • Replies: 4
    • Views: 1,349
    6th June 2003, 03:50 Go to last post
  11. Closed: vhdl model of risc architecture - link

    Started by politicante, 5th June 2003 21:13
    • Replies: 0
    • Views: 1,675
    5th June 2003, 21:13 Go to last post
  12. Closed: who uses dk1 and what are the impressions about it?

    Started by haifengyuyun, 4th June 2003 20:16
    • Replies: 1
    • Views: 1,312
    5th June 2003, 20:05 Go to last post
  13. Closed: Software for programming PAL

    Started by iberia, 5th June 2003 11:20
    • Replies: 1
    • Views: 1,711
    5th June 2003, 12:32 Go to last post
  14. Closed: Designing a Pulse Deinterleaving Circuit

    Started by Aircraft Maniac, 5th June 2003 07:30
    • Replies: 0
    • Views: 1,616
    5th June 2003, 07:30 Go to last post
  15. Closed: Designing of a 16 state convolutional Decoder

    Started by Aircraft Maniac, 5th June 2003 07:29
    • Replies: 0
    • Views: 1,332
    5th June 2003, 07:29 Go to last post
  16. Closed: Who has the sch of Altera Byteblaster II ?

    Started by cd505, 4th June 2003 02:25
    • Replies: 2
    • Views: 1,997
    4th June 2003, 20:00 Go to last post
  17. Closed: Can *C9572 Design Tri state

    Started by J_expoler2, 1st June 2003 03:50
    • Replies: 2
    • Views: 1,341
    2nd June 2003, 10:59 Go to last post
  18. Closed: how i design LIFO on FPGA

    Started by J_expoler2, 23rd May 2003 09:32
    • Replies: 3
    • Views: 2,185
    2nd June 2003, 02:49 Go to last post
  19. Closed: Looking for resources on 64b/65b encoding

    Started by it_boy, 30th May 2003 17:33
    • Replies: 0
    • Views: 2,171
    30th May 2003, 17:33 Go to last post
  20. Closed: Programmer for PA7540P ??

    Started by Myself, 30th May 2003 15:29
    • Replies: 0
    • Views: 1,214
    30th May 2003, 15:29 Go to last post
  21. Closed: How to use single macrocell in CPLD of xilinx?

    Started by cfxok, 27th May 2003 16:41
    • Replies: 2
    • Views: 1,621
    29th May 2003, 07:01 Go to last post
  22. Closed: iMPACT gives me xc9572_unsupported

    Started by kras, 7th May 2003 15:26
    • Replies: 5
    • Views: 2,291
    28th May 2003, 13:04 Go to last post
  23. Closed: IEEE.std_logic_misc.ALL

    Started by mcfly, 28th May 2003 04:48
    • Replies: 2
    • Views: 3,922
    28th May 2003, 10:36 Go to last post
  24. Closed: the clock of Xilinx Vetex2 FPGA?

    Started by lvwx, 26th May 2003 14:52
    • Replies: 2
    • Views: 1,655
    27th May 2003, 02:48 Go to last post
  25. Closed: Timing simulation of two FPGA

    Started by irum4, 26th May 2003 14:33
    • Replies: 0
    • Views: 1,188
    26th May 2003, 14:33 Go to last post
  26. Closed: JHDL - link and recommendation

    Started by Ohh, 26th May 2003 10:09
    • Replies: 0
    • Views: 1,362
    26th May 2003, 10:09 Go to last post
  27. Closed: PCM-to-NRZ, NRZ-to-PCM - how?

    Started by Laplace, 25th May 2003 01:42
    • Replies: 1
    • Views: 1,592
    25th May 2003, 08:40 Go to last post
  28. Closed: Using internal oscilator on an FPGA

    Started by happytronic, 24th May 2003 17:13
    • Replies: 2
    • Views: 2,076
    24th May 2003, 17:33 Go to last post
  29. Closed: Schmitt input for xilinx's spartan2 design.

    Started by zcq, 24th April 2003 04:06
    • Replies: 8
    • Views: 2,802
    24th May 2003, 16:25 Go to last post
  30. Closed: How to calculate FPGA MIPS ?

    Started by Bartart, 22nd May 2003 12:20
    • Replies: 1
    • Views: 3,013
    23rd May 2003, 19:04 Go to last post