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Threads 21721 to 21750 of 22099

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Xilinx 9500 series CPLD PWM code problem

    Started by Mercury, 7th October 2003 20:13
    • Replies: 3
    • Views: 3,449
    9th October 2003, 11:32 Go to last post
  2. Closed: Implementing lvds mega function

    Started by sul, 28th September 2003 21:30
    • Replies: 1
    • Views: 1,545
    8th October 2003, 10:20 Go to last post
  3. Closed: How to build a programmer for ALTERA EPM7256EQC160-12 ?

    Started by sunjimmy, 5th October 2003 17:51
    • Replies: 4
    • Views: 1,615
    8th October 2003, 07:29 Go to last post
  4. Closed: HOw to split bus in FPGA Adv using "Block Diagram' ent

    Started by always@smart, 3rd October 2003 16:19
    • Replies: 3
    • Views: 1,785
    7th October 2003, 16:32 Go to last post
  5. Closed: Using PAL/GAL as 74C926 IC

    Started by killex, 6th October 2003 12:10
    • Replies: 3
    • Views: 3,135
    6th October 2003, 17:37 Go to last post
  6. Closed: USB H0st c0ntr0ller design with VHDL code

    Started by leechk, 10th September 2003 10:27
    • Replies: 5
    • Views: 3,508
    6th October 2003, 14:38 Go to last post
  7. Closed: Problem with installing PCI-cards

    Started by irum4, 6th October 2003 14:24
    • Replies: 0
    • Views: 1,330
    6th October 2003, 14:24 Go to last post
  8. Closed: Whats the most popular fpga device and how to program it?

    Started by ash, 30th September 2003 21:35
    • Replies: 6
    • Views: 3,084
    6th October 2003, 03:44 Go to last post
  9. Closed: what're pal,gal,pld,spld,cpld,peel,fpga and asic?

    Started by ash, 22nd September 2003 21:32
    • Replies: 3
    • Views: 5,254
    6th October 2003, 03:19 Go to last post
  10. Closed: Shematic Symbols and Layout footprints of Xilinx Devices?

    Started by massive, 5th October 2003 22:30
    • Replies: 0
    • Views: 1,849
    5th October 2003, 22:30 Go to last post
  11. Closed: Xilinx Spartan2 BlockRAM initialisation ?

    Started by CADDevil, 3rd October 2003 21:27
    • Replies: 2
    • Views: 2,350
    4th October 2003, 23:58 Go to last post
  12. Closed: PCI Card design - which one do you advise?

    Started by mystery, 24th July 2003 07:32
    • Replies: 14
    • Views: 2,423
    3rd October 2003, 18:31 Go to last post
  13. Closed: Propic2 XP help please. It wont work for Winxp

    Started by challenger, 29th September 2003 22:07
    • Replies: 6
    • Views: 4,227
    3rd October 2003, 08:43 Go to last post
  14. Closed: Help on ISP for XC95108-PQ100

    Started by vkchau, 3rd October 2003 04:08
    • Replies: 2
    • Views: 1,480
    3rd October 2003, 08:41 Go to last post
  15. Closed: Connecting CPLD to optical switch

    Started by sul, 29th September 2003 21:03
    • Replies: 7
    • Views: 1,563
    2nd October 2003, 22:49 Go to last post
  16. Closed: How to use Aldec ActiveHDL to develop 16V8 architecture?

    Started by elektryk, 2nd October 2003 19:54
    • Replies: 1
    • Views: 1,569
    2nd October 2003, 21:19 Go to last post
  17. Closed: AVR core from Opencores - syntax errors ?

    Started by CADDevil, 2nd October 2003 21:13
    • Replies: 0
    • Views: 1,506
    2nd October 2003, 21:13 Go to last post
  18. Closed: FPGA in pcmcia card. How to tackle the current limit?

    Started by dll_embed, 2nd October 2003 10:53
    • Replies: 1
    • Views: 1,528
    2nd October 2003, 15:40 Go to last post
  19. Closed: How to stimulate the bus occupation in PCI-PC applications?

    Started by zape, 19th July 2003 12:10
    • Replies: 9
    • Views: 2,092
    2nd October 2003, 13:53 Go to last post
  20. Closed: How to do post-synthesis simulation for A|ter@ FPGA??

    Started by always@smart, 2nd October 2003 10:30
    • Replies: 1
    • Views: 1,634
    2nd October 2003, 11:17 Go to last post
  21. Closed: CADENCE SPECTRAQUEST 14.XX TRAINING MANUAL HELP

    Started by concat, 2nd October 2003 10:31
    • Replies: 0
    • Views: 1,567
    2nd October 2003, 10:31 Go to last post
  22. Closed: Mode/s!m Force, noforce problems.

    Started by jelydonut, 10th September 2003 15:11
    • Replies: 9
    • Views: 2,302
    1st October 2003, 13:10 Go to last post
  23. Closed: NEED HELP: Optimized blocks in VHDL design

    Started by avd, 30th September 2003 12:13
    • Replies: 1
    • Views: 1,238
    1st October 2003, 07:48 Go to last post
  24. Closed: a problem about simulation in quartus ii 3.0

    Started by deebar, 29th August 2003 04:19
    • Replies: 2
    • Views: 2,037
    1st October 2003, 07:47 Go to last post
  25. Closed: Developing DVI receiver on Altera FPGA

    Started by Acido Cinico, 27th September 2003 13:06
    • Replies: 3
    • Views: 4,257
    30th September 2003, 08:21 Go to last post
  26. Closed: digital filters - what are they?

    Started by sajeev_antony, 29th September 2003 13:42
    • Replies: 2
    • Views: 1,918
    29th September 2003, 20:27 Go to last post
  27. Closed: How can I burn a cpld with a core?

    Started by 7rots51, 28th September 2003 14:37
    • Replies: 6
    • Views: 1,794
    29th September 2003, 17:55 Go to last post
  28. Closed: how to encrypt IP core used for FPGA?

    Started by FLEXcertifydll, 4th September 2003 10:11
    • Replies: 10
    • Views: 2,919
    29th September 2003, 16:54 Go to last post
  29. Closed: Ifft for dvb-t - looking for an algorithm

    Started by farshid1354, 14th June 2003 10:57
    • Replies: 2
    • Views: 2,290
    29th September 2003, 10:30 Go to last post
  30. Closed: Virtex-II pro Dev board - looking for schematics

    Started by it_boy, 24th September 2003 14:28
    • Replies: 3
    • Views: 2,553
    28th September 2003, 09:23 Go to last post