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Threads 21661 to 21690 of 22101

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: sample of vhdl code for GPIB !!

    Started by ivanHsieh, 19th November 2003 01:34
    • Replies: 0
    • Views: 2,808
    19th November 2003, 01:34 Go to last post
  2. Closed: interface NAND flash with PCI target core?

    Started by catrat, 17th November 2003 14:32
    • Replies: 1
    • Views: 2,025
    18th November 2003, 07:39 Go to last post
  3. Closed: message error in modelsim xe starter 5.6a and in ise 5.1

    Started by bluesman, 17th November 2003 23:46
    • Replies: 0
    • Views: 1,711
    17th November 2003, 23:46 Go to last post
  4. Closed: algorythm behind Data Encryption Standard?

    Started by wasp, 30th October 2003 12:03
    • Replies: 4
    • Views: 1,720
    16th November 2003, 13:43 Go to last post
  5. Closed: HELP: HOW TO generate such timing

    Started by arena_yang, 12th November 2003 08:58
    • Replies: 2
    • Views: 1,091
    15th November 2003, 04:16 Go to last post
  6. Closed: Help me build a FPGA based load balancer

    Started by netwizio, 14th November 2003 20:39
    • Replies: 0
    • Views: 1,481
    14th November 2003, 20:39 Go to last post
  7. Closed: Xilinx Impact gives error when FPGA is configured Via JTAG

    Started by auromira, 6th January 2003 16:50
    • Replies: 16
    • Views: 7,385
    14th November 2003, 10:20 Go to last post
  8. Closed: FPGA digital video developer boards

    Started by jetal, 12th September 2003 11:31
    • Replies: 1
    • Views: 1,497
    13th November 2003, 06:34 Go to last post
  9. Closed: what is Distributed Arithmetic

    Started by J_expoler2, 13th November 2003 04:02
    • Replies: 0
    • Views: 1,329
    13th November 2003, 04:02 Go to last post
  10. Closed: Good free Pic core and tutorial

    Started by al_extreme, 11th November 2003 12:22
    • Replies: 4
    • Views: 3,070
    12th November 2003, 04:05 Go to last post
  11. Closed: Problem with updating Xilinx to ver. 5.2

    Started by ASIC, 10th November 2003 06:58
    • Replies: 5
    • Views: 2,171
    11th November 2003, 01:16 Go to last post
  12. Closed: EP1C12Q240 cyclone - minimum a number of board layers

    Started by spit, 23rd October 2003 10:52
    • Replies: 2
    • Views: 2,208
    10th November 2003, 16:42 Go to last post
  13. Closed: How do I use Block RAM in my spartanII based design?

    Started by Vonn, 5th November 2003 09:07
    • Replies: 8
    • Views: 3,060
    10th November 2003, 11:44 Go to last post
  14. Closed: Help: Implement design warnings (FPGA)

    Started by avd, 7th October 2003 14:10
    • Replies: 2
    • Views: 1,548
    10th November 2003, 01:28 Go to last post
  15. Closed: What is the best software for Verilog?

    Started by 7rots51, 8th November 2003 17:39
    • Replies: 2
    • Views: 1,303
    9th November 2003, 19:16 Go to last post
  16. Closed: Toogle bit signal on ModelSim?

    Started by cb30, 29th October 2003 05:51
    • Replies: 1
    • Views: 1,286
    9th November 2003, 08:34 Go to last post
  17. Closed: No DLY file when using ISE 6.1i

    Started by echo47, 25th October 2003 08:52
    • Replies: 3
    • Views: 1,734
    6th November 2003, 10:40 Go to last post
  18. Closed: size of HDLC core of 0pencore

    Started by 7rots51, 5th November 2003 14:11
    • Replies: 0
    • Views: 1,516
    5th November 2003, 14:11 Go to last post
  19. Closed: Looking for EPM7128SLC84-7 datasheet

    Started by 7rots51, 4th November 2003 11:14
    • Replies: 1
    • Views: 1,991
    4th November 2003, 15:34 Go to last post
  20. Closed: Parallel division in VHDL

    Started by sir-yuri, 4th November 2003 14:53
    • Replies: 0
    • Views: 3,100
    4th November 2003, 14:53 Go to last post
  21. Closed: NIOS and opencore ethmac?

    Started by catrat, 17th October 2003 09:35
    • Replies: 1
    • Views: 3,009
    4th November 2003, 03:22 Go to last post
  22. Closed: What generic connectors can be used with Rocket I/O?

    Started by it_boy, 27th October 2003 10:20
    • Replies: 5
    • Views: 2,425
    4th November 2003, 03:18 Go to last post
  23. Closed: few pin count but more gate array and FF stage

    Started by bunalmis, 2nd November 2003 16:52
    • Replies: 1
    • Views: 1,268
    3rd November 2003, 20:57 Go to last post
  24. Closed: how can I make the power cost lower?

    Started by mrhfw, 1st November 2003 23:43
    • Replies: 2
    • Views: 1,188
    3rd November 2003, 20:52 Go to last post
  25. Closed: Convertion of designs from Quartus to ISE

    Started by twinsen, 2nd November 2003 18:28
    • Replies: 1
    • Views: 1,474
    3rd November 2003, 00:08 Go to last post
  26. Closed: Help me with controlling 3 DC Motors using a GAL

    Started by goosiegoo, 1st November 2003 18:06
    • Replies: 1
    • Views: 1,919
    2nd November 2003, 07:12 Go to last post
  27. Closed: Video Scaler/Deinterlacer

    Started by lucbra, 30th October 2003 21:57
    • Replies: 0
    • Views: 2,102
    30th October 2003, 21:57 Go to last post
  28. Closed: FPGA Design tools: Plan*Ahead from H.i.e.r*Design

    Started by TurboPC, 30th October 2003 06:27
    • Replies: 0
    • Views: 956
    30th October 2003, 06:27 Go to last post
  29. Closed: Can you do LCD driver with a keypad using CPLD?

    Started by ZeleC, 23rd October 2003 18:40
    • Replies: 3
    • Views: 3,374
    28th October 2003, 16:47 Go to last post
  30. Closed: Modelsim - how to reset flip-flops ?

    Started by CADDevil, 28th October 2003 00:52
    • Replies: 3
    • Views: 2,469
    28th October 2003, 02:45 Go to last post