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Threads 21511 to 21540 of 22009

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Does anybody knows about new Altera 'Tsunami' Devices?

    Started by Black Jack, 14th December 2003 14:44
    • Replies: 2
    • Views: 1,335
    15th December 2003, 08:11 Go to last post
  2. Closed: How to write ROM data and insert it into vhdl code?

    Started by junchaoguo51888, 14th December 2003 08:42
    • Replies: 2
    • Views: 2,241
    15th December 2003, 07:34 Go to last post
  3. Closed: I need evalution version of MAC core written by Xilinx

    Started by dariush, 14th December 2003 13:43
    • Replies: 0
    • Views: 1,120
    14th December 2003, 13:43 Go to last post
  4. Closed: How to create a macro in xilinx and use it?

    Started by samuel_john, 9th December 2003 12:49
    • Replies: 1
    • Views: 1,753
    13th December 2003, 06:40 Go to last post
  5. Closed: maximum frequency of clock in MAX7128SLC84-10

    Started by kkdelabaca, 12th December 2003 14:15
    • Replies: 3
    • Views: 1,880
    12th December 2003, 17:24 Go to last post
  6. Closed: Differences between EPM7128SLC84-10 and EPM7128ELC-10

    Started by kkdelabaca, 12th December 2003 14:48
    • Replies: 2
    • Views: 1,882
    12th December 2003, 16:33 Go to last post
  7. Closed: How to make a big delay in VHDL code?

    Started by ZeleC, 13th November 2003 19:51
    • Replies: 13
    • Views: 5,116
    12th December 2003, 09:53 Go to last post
  8. Closed: Spartan III development board

    Started by must, 11th December 2003 12:21
    • Replies: 6
    • Views: 1,939
    11th December 2003, 20:56 Go to last post
  9. Closed: I need datasheet of MT88L70

    Started by scorpionss, 10th December 2003 18:45
    • Replies: 4
    • Views: 1,471
    11th December 2003, 20:01 Go to last post
  10. Closed: VHDL based design methodology

    Started by Al Farouk, 11th December 2003 12:33
    • Replies: 0
    • Views: 1,053
    11th December 2003, 12:33 Go to last post
  11. Closed: Why synopsys gives up the FE?

    Started by PowerEDA2003, 21st February 2003 16:53
    • Replies: 4
    • Views: 1,832
    11th December 2003, 10:42 Go to last post
  12. Closed: May a CPLD have 3 clock input? these clock is not relevant.

    Started by wwwrabbit, 1st December 2003 18:43
    • Replies: 5
    • Views: 2,085
    10th December 2003, 22:05 Go to last post
  13. Closed: I only have 61.44Mhz clock, how can I get 2Hz and 20Hz clock

    Started by yerics, 3rd December 2003 03:35
    • Replies: 11
    • Views: 2,992
    10th December 2003, 15:59 Go to last post
  14. Closed: How can I know the maximum speed of an IP

    Started by Al Farouk, 9th December 2003 14:24
    • Replies: 4
    • Views: 1,658
    10th December 2003, 09:12 Go to last post
  15. Closed: [About]partial Reconfigurability in FPGA

    Started by GunSeed, 27th November 2003 04:44
    • Replies: 6
    • Views: 2,162
    10th December 2003, 09:06 Go to last post
  16. Closed: Measure the time period between 2 signals

    Started by Santos san, 8th December 2003 18:02
    • Replies: 2
    • Views: 1,873
    9th December 2003, 18:15 Go to last post
  17. Closed: How to see the waveform of intermedia signals in MaxPlus

    Started by wwwrabbit, 7th December 2003 00:00
    • Replies: 4
    • Views: 2,046
    9th December 2003, 09:59 Go to last post
  18. Closed: How many inputs can be driven by a FF in a FPGA?

    Started by samuel_john, 6th December 2003 09:47
    • Replies: 1
    • Views: 1,480
    9th December 2003, 06:23 Go to last post
  19. Closed: assign group signals in MaxPlus?

    Started by wwwrabbit, 4th December 2003 23:45
    • Replies: 4
    • Views: 1,790
    8th December 2003, 13:19 Go to last post
  20. Closed: Help - How can I translate 3.3V(SpartanII) to a 15V(CMOS)

    Started by jonatan, 7th December 2003 13:28
    • Replies: 2
    • Views: 1,773
    7th December 2003, 16:10 Go to last post
  21. Closed: Advice about Color Interpolation

    Started by kunjalan, 7th December 2003 15:27
    • Replies: 0
    • Views: 1,160
    7th December 2003, 15:27 Go to last post
  22. Closed: What is a clock jitter and when does it occur?

    Started by samuel_john, 3rd December 2003 12:06
    • Replies: 12
    • Views: 3,929
    5th December 2003, 15:39 Go to last post
  23. Closed: Spartan 2 configuration method

    Started by r_e_m_y, 4th December 2003 09:13
    • Replies: 6
    • Views: 2,070
    5th December 2003, 13:24 Go to last post
  24. Closed: How to assign pin in graphics mode for that clk_raw signal?

    Started by senthilkumar, 5th December 2003 08:00
    • Replies: 2
    • Views: 1,585
    5th December 2003, 09:35 Go to last post
  25. Closed: how to constrain these clocks ?

    Started by handsome, 22nd November 2003 12:04
    • Replies: 9
    • Views: 5,430
    4th December 2003, 06:17 Go to last post
  26. Closed: How to implement a dsp in vlsi or fpga?

    Started by saichom, 4th December 2003 02:45
    • Replies: 1
    • Views: 2,064
    4th December 2003, 03:06 Go to last post
  27. Closed: What are the different types of ic packaging?

    Started by asic1984, 3rd December 2003 13:21
    • Replies: 1
    • Views: 2,139
    3rd December 2003, 13:42 Go to last post
  28. Closed: Any books regarding to systemC

    Started by roadrunner, 25th September 2003 16:41
    • Replies: 3
    • Views: 1,858
    3rd December 2003, 06:02 Go to last post
  29. Closed: INFO: Universal JTAG SCAN is here

    Started by Black Jack, 2nd December 2003 14:00
    • Replies: 0
    • Views: 1,755
    2nd December 2003, 14:00 Go to last post
  30. Closed: Looking for samples for CPLD or FPGA

    Started by jochez, 16th November 2003 22:06
    • Replies: 4
    • Views: 3,407
    2nd December 2003, 10:51 Go to last post