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Threads 1531 to 1560 of 21842

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: A concept about State Machine using process in VHDL

    Started by beginner_EDA, 17th November 2015 17:10
    • Replies: 16
    • Views: 879
    20th November 2015, 06:15 Go to last post
  2. Closed: VSS-Monitoring ethernet trailer

    Started by beginner_EDA, 12th November 2015 09:40
    • Replies: 4
    • Views: 6,074
    19th November 2015, 17:03 Go to last post
  3. Closed: survey on UART 16550 IP

    Started by sanjeev85, 19th November 2015 13:37
    • Replies: 1
    • Views: 343
    19th November 2015, 15:52 Go to last post
  4. Closed: c_ver failed generated Verilog file

    Started by bhliuliu, 19th November 2015 04:34
    • Replies: 0
    • Views: 739
    19th November 2015, 04:34 Go to last post
  5. Closed: Error in DFlipFlop Placement constraint in VHDL Code

    Started by msdarvishi, 18th November 2015 19:53
    • Replies: 1
    • Views: 339
    18th November 2015, 22:51 Go to last post
  6. Closed: Avalon SPI Interface with QSYS

    Started by Hugo17, 18th November 2015 13:31
    • Replies: 0
    • Views: 697
    18th November 2015, 13:31 Go to last post
    • Replies: 1
    • Views: 508
    18th November 2015, 03:10 Go to last post
    • Replies: 2
    • Views: 2,185
    18th November 2015, 01:08 Go to last post
  7. Closed: SystemC differential clock

    Started by linux-dude, 28th October 2015 12:10
    • Replies: 2
    • Views: 7,419
    17th November 2015, 19:12 Go to last post
  8. Closed: How to decrease synthesize, Map and Place&Route Time?

    Started by Port Map, 16th November 2015 16:59
    • Replies: 6
    • Views: 446
    17th November 2015, 16:12 Go to last post
  9. Closed: Suggest device for 100+ FPS camera board

    Started by prateek_k_chd, 16th November 2015 07:54
    • Replies: 9
    • Views: 562
    17th November 2015, 06:52 Go to last post
    • Replies: 3
    • Views: 592
    17th November 2015, 03:08 Go to last post
  10. Closed: VHDL simple calculator

    Started by Richard Keno Garvey, 17th November 2015 01:36
    • Replies: 4
    • Views: 1,016
    17th November 2015, 02:52 Go to last post
  11. Closed: Vivado 2015.2..........................

    Started by velu.plg, 16th November 2015 10:02
    • Replies: 1
    • Views: 418
    16th November 2015, 19:35 Go to last post
  12. Closed: Using De2-115 board to run a project developed on a different board?

    Started by newbie99, 15th November 2015 14:59
    • Replies: 2
    • Views: 457
    15th November 2015, 16:02 Go to last post
  13. Closed: FPGA Low Pass Filter Design with Spartan 3E Starter KIT

    Started by khoanguyenngo, 14th November 2015 11:21
    • Replies: 1
    • Views: 407
    14th November 2015, 18:03 Go to last post
    • Replies: 2
    • Views: 1,099
    14th November 2015, 16:33 Go to last post
  14. Closed: Segmentation Error in Precision

    Started by muhammad_ali, 13th November 2015 19:46
    • Replies: 1
    • Views: 508
    14th November 2015, 08:03 Go to last post
  15. Closed: mcode block in system generator

    Started by prashanthi999, 13th November 2015 15:01
    • Replies: 0
    • Views: 291
    13th November 2015, 15:01 Go to last post
  16. Closed: How to Obtain Overhead of a Specific Module in ISE?

    Started by msdarvishi, 12th November 2015 23:54
    • Replies: 1
    • Views: 355
    13th November 2015, 07:30 Go to last post
  17. Closed: fpga programer for spartan3 familiy

    Started by shayanbaro, 11th November 2015 14:11
    • Replies: 1
    • Views: 400
    13th November 2015, 00:14 Go to last post
  18. Closed: mcode block path in system generator

    Started by prashanthi999, 12th November 2015 19:05
    • Replies: 0
    • Views: 385
    12th November 2015, 19:05 Go to last post
  19. Closed: Cyclone 4 JTAG programming issue

    Started by sherif123, 11th November 2015 16:45
    • Replies: 2
    • Views: 430
    12th November 2015, 16:49 Go to last post
  20. Closed: how is bram accesses characterized?

    Started by milan.km, 11th November 2015 16:39
    • Replies: 3
    • Views: 358
    11th November 2015, 19:13 Go to last post
  21. Closed: Concepts of Synchronization

    Started by aravind9, 11th November 2015 13:29
    • Replies: 1
    • Views: 311
    11th November 2015, 13:56 Go to last post
  22. Closed: How to calculate Latency of a PID block designed in VHDL

    Started by areebaa, 11th November 2015 03:52
    • Replies: 6
    • Views: 501
    11th November 2015, 08:29 Go to last post
  23. Closed: Why var is not taking value as per constraint

    Started by jdshah, 10th November 2015 14:54
    • Replies: 5
    • Views: 483
    11th November 2015, 04:29 Go to last post
  24. Closed: Simulate a USB mouse (using USB protocol)

    Started by franofcholet, 10th November 2015 14:32
    • Replies: 1
    • Views: 491
    10th November 2015, 15:27 Go to last post
  25. Closed: can clk multiplleing be done by DCM?

    Started by milan.km, 9th November 2015 08:29
    2 Pages
    1 2
    • Replies: 22
    • Views: 973
    9th November 2015, 21:31 Go to last post
  26. Closed: Display content in lpm rom to VGA monitor

    Started by Milenia, 9th November 2015 17:41
    • Replies: 1
    • Views: 371
    9th November 2015, 18:04 Go to last post