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Threads 1531 to 1560 of 21959

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: Help on seed for true random generator in VHDL

    Started by LatticeSemiconductor, 18th January 2016 11:51
    • Replies: 4
    • Views: 1,113
    18th January 2016, 13:57 Go to last post
  2. Closed: Verilog code for module required to design DCO

    Started by niteshtripathi, 17th January 2016 14:48
    • Replies: 1
    • Views: 566
    17th January 2016, 18:23 Go to last post
  3. Closed: xilinx - ISE : other XST command line options

    Started by amirke, 12th January 2016 17:58
    • Replies: 7
    • Views: 1,123
    16th January 2016, 18:16 Go to last post
  4. Closed: Tutorial for Xilinx Coregen

    Started by garvind25, 16th January 2016 02:22
    • Replies: 3
    • Views: 459
    16th January 2016, 13:04 Go to last post
  5. Closed: VHDL version supported by Xilinx ISE

    Started by garvind25, 15th January 2016 15:16
    • Replies: 15
    • Views: 1,370
    16th January 2016, 02:14 Go to last post
  6. Closed: editing VHDL source file for AXI EMC v3.0 IP core

    Started by Sunayana Chakradhar, 15th January 2016 05:59
    • Replies: 7
    • Views: 575
    15th January 2016, 17:48 Go to last post
  7. Closed: Dual Clock FIFO for clock crossing of continuos data

    Started by flote21, 11th January 2016 01:58
    • Replies: 18
    • Views: 1,137
    15th January 2016, 12:33 Go to last post
  8. Closed: Preparation of a Microblaze System for production.

    Started by Yosmany325, 13th January 2016 15:18
    • Replies: 1
    • Views: 535
    14th January 2016, 19:03 Go to last post
  9. Closed: Differences between front end design for ASIC and FPGA

    Started by sun_ray, 12th January 2016 19:41
    • Replies: 2
    • Views: 531
    12th January 2016, 22:38 Go to last post
    • Replies: 0
    • Views: 382
    12th January 2016, 10:39 Go to last post
  10. Closed: AXI EMC v3.0 IP core

    Started by Sunayana Chakradhar, 8th January 2016 08:06
    • Replies: 4
    • Views: 689
    12th January 2016, 07:58 Go to last post
  11. Closed: 128b/132b encoding and decoding

    Started by sh.akhtari, 9th January 2016 21:26
    • Replies: 1
    • Views: 1,602
    11th January 2016, 19:44 Go to last post
  12. Closed: How to output design internal signal directly to FPGA IO?

    Started by pandayeah, 9th January 2016 04:11
    • Replies: 2
    • Views: 432
    11th January 2016, 19:33 Go to last post
  13. Closed: FPGA programmer selection help

    Started by Electronics_chaitanya, 8th January 2016 13:55
    • Replies: 4
    • Views: 756
    11th January 2016, 18:02 Go to last post
  14. [SOLVED]Closed: Xilinx ISE ERROR:Xst:2369 - Empty project file "C:\xxxx" what is it about?

    Started by Alper özel, 8th January 2016 10:43
    • Replies: 5
    • Views: 1,411
    11th January 2016, 17:56 Go to last post
  15. Closed: saif file format made by ISE

    Started by Ssepehri, 10th January 2016 18:53
    • Replies: 0
    • Views: 567
    10th January 2016, 18:53 Go to last post
  16. Closed: problem in access one bit of array

    Started by digital design, 9th January 2016 17:56
    • Replies: 8
    • Views: 573
    10th January 2016, 08:11 Go to last post
  17. Closed: [Moved]: Pre RTL pin planning

    Started by Sunayana Chakradhar, 9th January 2016 13:26
    • Replies: 0
    • Views: 533
    9th January 2016, 13:26 Go to last post
  18. Closed: External clock for zynq 7020

    Started by Sunayana Chakradhar, 8th January 2016 15:19
    • Replies: 2
    • Views: 522
    8th January 2016, 17:34 Go to last post
  19. Closed: How to test the speed grade of the FPGA

    Started by bjzhangwn, 6th January 2016 17:09
    • Replies: 3
    • Views: 507
    6th January 2016, 19:56 Go to last post
  20. Closed: What is difference between below two code execution

    Started by jdshah, 6th January 2016 14:28
    • Replies: 1
    • Views: 337
    6th January 2016, 17:43 Go to last post
  21. Closed: PHY, SerdEs, PLL in FPGA

    Started by sun_ray, 6th January 2016 11:16
    • Replies: 3
    • Views: 505
    6th January 2016, 17:33 Go to last post
  22. Closed: Enable JTAG WINCUPL CPLD

    Started by camius, 6th January 2016 16:27
    • Replies: 3
    • Views: 604
    6th January 2016, 17:00 Go to last post
  23. Closed: CAN Protocol to FPGA

    Started by Elhb, 4th January 2016 14:32
    • Replies: 6
    • Views: 783
    5th January 2016, 17:00 Go to last post
  24. Closed: Request: Fault injection tools in fpga

    Started by Zerox100, 3rd January 2016 19:16
    • Replies: 0
    • Views: 469
    3rd January 2016, 19:16 Go to last post
  25. Closed: Interface shared SRAM and flash on Zynq

    Started by Sunayana Chakradhar, 1st January 2016 16:04
    • Replies: 2
    • Views: 662
    3rd January 2016, 14:38 Go to last post
  26. Closed: FPGA kit with MP3 hardware decoder

    Started by muhammad_ali, 2nd January 2016 19:22
    • Replies: 0
    • Views: 496
    2nd January 2016, 19:22 Go to last post
  27. Closed: Pins on the Zynq FPGA

    Started by Sunayana Chakradhar, 1st January 2016 16:11
    • Replies: 1
    • Views: 1,373
    2nd January 2016, 19:21 Go to last post
  28. Closed: Debouncer & FIFO in VHDL

    Started by Morell, 29th December 2015 11:49
    • Replies: 7
    • Views: 833
    1st January 2016, 12:50 Go to last post
  29. Moved: Transmitter & Debouncer in VHDL

    Started by Morell, 1st January 2016 14:54
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