1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    103,462
Page 52 of 737 FirstFirst ... 2 42 50 51 52 53 54 62 102 152 552 ... LastLast
Threads 1531 to 1560 of 22099

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Simulation tool for FPGA based systems

    Started by garvind25, 17th March 2016 08:50
    • Replies: 4
    • Views: 795
    21st March 2016, 15:16 Go to last post
  2. Closed: Power sequence cyclone v

    Started by nsgil85, 21st March 2016 08:45
    • Replies: 4
    • Views: 881
    21st March 2016, 15:15 Go to last post
  3. [SOLVED]Closed: VHDL - Combinatorial feedback loops in JK FF but not in D FF

    Started by arnoldwbush, 20th March 2016 10:13
    • Replies: 9
    • Views: 1,054
    21st March 2016, 14:58 Go to last post
  4. Closed: error loading design in Model Sim

    Started by moin_moin, 20th March 2016 21:11
    • Replies: 1
    • Views: 1,262
    20th March 2016, 21:29 Go to last post
  5. Closed: Calculator schematic circuit

    Started by bbb10, 18th March 2016 21:41
    • Replies: 3
    • Views: 766
    19th March 2016, 18:12 Go to last post
  6. Closed: understanding verilog code

    Started by exceeder88, 15th March 2016 11:07
    • Replies: 7
    • Views: 1,152
    18th March 2016, 20:58 Go to last post
    • Replies: 3
    • Views: 673
    18th March 2016, 20:43 Go to last post
  7. Closed: generic default values in vhdl

    Started by Binome, 18th March 2016 09:29
    • Replies: 3
    • Views: 746
    18th March 2016, 13:37 Go to last post
  8. Closed: SPI slave to parallel out - a little help please!

    Started by Mark Baseggio, 15th March 2016 19:11
    2 Pages
    1 2
    • Replies: 20
    • Views: 1,561
    18th March 2016, 00:22 Go to last post
  9. Closed: How to pass a (generic) parameter to different blocks?

    Started by Hugo17, 15th March 2016 10:31
    • Replies: 1
    • Views: 447
    17th March 2016, 23:07 Go to last post
  10. Closed: 4 bit to 8 bit ALU conversion

    Started by Proton01, 17th March 2016 14:52
    • Replies: 2
    • Views: 608
    17th March 2016, 15:34 Go to last post
  11. Closed: hread command in vhdl

    Started by 214, 17th March 2016 09:26
    • Replies: 5
    • Views: 1,161
    17th March 2016, 14:25 Go to last post
  12. Closed: Assigning Notepad ++ as the default text editor for Vivado

    Started by shaiko, 17th March 2016 12:38
    • Replies: 1
    • Views: 1,350
    17th March 2016, 13:09 Go to last post
  13. Closed: To implement snack vending machine

    Started by shubham121, 16th March 2016 20:27
    • Replies: 2
    • Views: 507
    17th March 2016, 10:13 Go to last post
  14. Closed: Is it safe to use 2 FIFOs

    Started by shaiko, 16th March 2016 09:58
    • Replies: 14
    • Views: 763
    17th March 2016, 04:41 Go to last post
  15. Closed: Change a front of clock signal

    Started by ustinoff, 15th March 2016 17:20
    • Replies: 7
    • Views: 623
    16th March 2016, 05:36 Go to last post
  16. Closed: ALU 4 bit data multiplexer

    Started by jessilen, 15th March 2016 21:15
    • Replies: 1
    • Views: 549
    15th March 2016, 23:24 Go to last post
    • Replies: 0
    • Views: 485
    15th March 2016, 17:58 Go to last post
  17. Closed: 10-Bit Counter in Altera DE1 using Verilog

    Started by nizdom, 13th March 2016 13:42
    • Replies: 6
    • Views: 1,204
    15th March 2016, 12:35 Go to last post
  18. Closed: Process in VHDL code

    Started by MSAKARIM, 14th March 2016 17:22
    • Replies: 7
    • Views: 678
    15th March 2016, 10:38 Go to last post
  19. Closed: How to test the fpga base array?

    Started by bjzhangwn, 14th March 2016 16:23
    • Replies: 2
    • Views: 515
    15th March 2016, 09:16 Go to last post
  20. Closed: Verilog assign &

    Started by shaiko, 14th March 2016 09:17
    • Replies: 6
    • Views: 574
    14th March 2016, 22:05 Go to last post
  21. Closed: how to give a variable array in vhdl for papilio one

    Started by fisat, 14th March 2016 09:41
    • Replies: 1
    • Views: 424
    14th March 2016, 10:40 Go to last post
  22. Closed: Choosing between matlab and simulink

    Started by Sunayana Chakradhar, 11th March 2016 16:49
    • Replies: 4
    • Views: 551
    12th March 2016, 13:36 Go to last post
  23. Closed: Designing a packet processor on the FPGA ZC7020

    Started by Sunayana Chakradhar, 11th March 2016 17:02
    • Replies: 3
    • Views: 463
    12th March 2016, 08:24 Go to last post
  24. Closed: Using generics in VHDL modules

    Started by Binome, 10th March 2016 11:44
    • Replies: 5
    • Views: 585
    12th March 2016, 03:45 Go to last post
  25. Closed: 4 bit up down counter with programmable modulo value

    Started by amd1416, 9th March 2016 16:15
    • Replies: 18
    • Views: 1,645
    11th March 2016, 18:58 Go to last post
  26. Closed: An strange error message : ERROR:Anno:169

    Started by msdarvishi, 10th March 2016 18:43
    • Replies: 2
    • Views: 515
    10th March 2016, 23:30 Go to last post
  27. Closed: Multi-core simulation in Modelsim

    Started by ustinoff, 8th March 2016 20:08
    • Replies: 13
    • Views: 1,984
    10th March 2016, 08:15 Go to last post
  28. Closed: DDR DATA Sampling method

    Started by nsgil85, 8th March 2016 09:06
    • Replies: 3
    • Views: 482
    8th March 2016, 10:39 Go to last post