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Threads 1501 to 1530 of 21681

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: how to determine the relevent msb bit in a 32 bit stream

    Started by Ashish Agrawal, 20th September 2015 06:53
    • Replies: 5
    • Views: 710
    22nd September 2015, 14:15 Go to last post
  2. Closed: Different widths of data on same bus

    Started by rac70, 15th September 2015 06:56
    • Replies: 8
    • Views: 581
    22nd September 2015, 12:53 Go to last post
  3. Closed: Altera Cyclone IV single chip power suppy.

    Started by flote21, 18th September 2015 13:56
    • Replies: 2
    • Views: 561
    21st September 2015, 14:00 Go to last post
  4. Closed: can we generate sine wave in fpga without look up tables

    Started by hulk789, 19th September 2015 14:43
    • Replies: 9
    • Views: 956
    21st September 2015, 10:08 Go to last post
  5. [SOLVED]Closed: Bit swapping in Verilog

    Started by andre_teprom, 20th September 2015 17:29
    • Replies: 3
    • Views: 702
    20th September 2015, 20:50 Go to last post
  6. Closed: Can I use wavelet transform for video compression

    Started by kushal nandanwar, 20th September 2015 04:52
    • Replies: 3
    • Views: 465
    20th September 2015, 20:12 Go to last post
  7. Closed: [Moved] need verilog code for BSD( binary signed digit )adder

    Started by aampase, 19th September 2015 11:28
    • Replies: 0
    • Views: 601
    19th September 2015, 11:28 Go to last post
  8. Closed: how to write a tesbench with reading input from text and writting output in text?

    Started by milan.km, 14th September 2015 19:45
    2 Pages
    1 2
    • Replies: 32
    • Views: 1,541
    18th September 2015, 14:42 Go to last post
  9. Closed: fatal_error : simulator: fuse.cpp : 209:1.133

    Started by Furqan Ghoghari, 17th September 2015 09:28
    • Replies: 3
    • Views: 851
    18th September 2015, 08:09 Go to last post
  10. Closed: how to add multiple unsigned values?

    Started by milan.km, 17th September 2015 17:49
    • Replies: 2
    • Views: 428
    17th September 2015, 19:21 Go to last post
  11. Closed: Simulate DRAM on modelsim

    Started by nsgil85, 17th September 2015 12:14
    • Replies: 3
    • Views: 519
    17th September 2015, 18:43 Go to last post
  12. Closed: I am looking for VHDL code for digital filter

    Started by kushal nandanwar, 17th September 2015 17:28
    • Replies: 1
    • Views: 390
    17th September 2015, 17:38 Go to last post
  13. Closed: Altera u-boot -> what is this?

    Started by ivlsi, 17th September 2015 09:35
    • Replies: 1
    • Views: 386
    17th September 2015, 10:15 Go to last post
    • Replies: 3
    • Views: 1,380
    17th September 2015, 05:00 Go to last post
  14. Closed: FIR filter IPCore need 12 bit in out

    Started by h_rafii, 6th September 2015 14:01
    • Replies: 10
    • Views: 579
    17th September 2015, 02:22 Go to last post
  15. Closed: Bit Growth in digital designing

    Started by rezvania, 16th September 2015 05:42
    • Replies: 2
    • Views: 543
    16th September 2015, 07:47 Go to last post
    • Replies: 0
    • Views: 368
    15th September 2015, 18:20 Go to last post
  16. Closed: Implementing an AES cryptographic algorithm

    Started by Binome, 14th September 2015 08:36
    • Replies: 8
    • Views: 642
    15th September 2015, 16:57 Go to last post
  17. Closed: DDR Memory Address Granularity

    Started by shaiko, 23rd August 2015 12:11
    • Replies: 7
    • Views: 738
    15th September 2015, 09:48 Go to last post
  18. Closed: how to generate a queue for checking asynchronous fifo

    Started by sai685, 14th September 2015 12:17
    • Replies: 1
    • Views: 462
    15th September 2015, 05:06 Go to last post
  19. Closed: simulation can not read the text file?

    Started by milan.km, 14th September 2015 09:15
    • Replies: 5
    • Views: 487
    14th September 2015, 17:59 Go to last post
  20. Closed: has multiple drivers due to the non-tri-state driver

    Started by esielec, 13th September 2015 15:27
    • Replies: 1
    • Views: 1,090
    14th September 2015, 16:04 Go to last post
  21. [SOLVED]Closed: SystemVerilog Interfaces

    Started by keyboardcowboy, 13th September 2015 21:55
    • Replies: 1
    • Views: 1,824
    14th September 2015, 10:28 Go to last post
  22. Closed: HDLC 7E detection in 64-bit qword format - Design logic confusion

    Started by xtcx, 9th September 2015 13:30
    • Replies: 10
    • Views: 660
    14th September 2015, 05:59 Go to last post
  23. Closed: why types dont match?

    Started by JKR1, 13th September 2015 16:28
    • Replies: 4
    • Views: 430
    13th September 2015, 23:11 Go to last post
  24. Closed: how to work with fixed point libraries in ISE 13.2?

    Started by JKR1, 13th September 2015 12:40
    • Replies: 0
    • Views: 309
    13th September 2015, 12:40 Go to last post
  25. Closed: High speed board to board connection

    Started by Saltwater, 8th September 2015 17:15
    2 Pages
    1 2
    • Replies: 29
    • Views: 1,785
    12th September 2015, 20:37 Go to last post
  26. Closed: Error when compiling Xilinx IP in QuestaSim

    Started by paulgiro, 11th September 2015 17:17
    • Replies: 1
    • Views: 850
    12th September 2015, 06:28 Go to last post
  27. Closed: what is that warning mean while loading simulation?

    Started by JKR1, 11th September 2015 21:18
    • Replies: 2
    • Views: 380
    11th September 2015, 21:57 Go to last post
  28. [SOLVED]Closed: how to convert fixed points to the nearest std_logic_vector?

    Started by JKR1, 11th September 2015 13:08
    • Replies: 5
    • Views: 522
    11th September 2015, 20:28 Go to last post