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Threads 1501 to 1530 of 21555

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: Steaming Audio 44.1kHz Delta Sigma DAC --> FPGA

    Started by derrick_chi, 15th July 2015 20:31
    • Replies: 6
    • Views: 803
    4th August 2015, 21:12 Go to last post
  2. Closed: Xilinx XC3000 support

    Started by jamespond, 3rd August 2015 19:17
    • Replies: 2
    • Views: 491
    4th August 2015, 18:28 Go to last post
  3. Closed: PLL problem with declaration

    Started by davida, 4th August 2015 08:01
    • Replies: 14
    • Views: 723
    4th August 2015, 15:57 Go to last post
  4. Closed: VIRTEX 7 BLVDS Application

    Started by skquah, 26th July 2015 04:30
    • Replies: 2
    • Views: 491
    4th August 2015, 13:39 Go to last post
  5. Closed: Nexys 3 board seems to be failing

    Started by fahum, 2nd August 2015 11:51
    • Replies: 6
    • Views: 731
    4th August 2015, 10:43 Go to last post
    • Replies: 4
    • Views: 416
    4th August 2015, 09:47 Go to last post
  6. [SOLVED]Closed: array type can't be unconstained

    Started by nsgil85, 4th August 2015 08:18
    • Replies: 3
    • Views: 534
    4th August 2015, 09:42 Go to last post
    • Replies: 0
    • Views: 336
    4th August 2015, 07:51 Go to last post
  7. [SOLVED]Closed: Why don't Synplify Pro E-2010 generate mapped VHDL netlist?

    Started by Sumathigokul, 4th August 2015 06:41
    • Replies: 2
    • Views: 362
    4th August 2015, 07:11 Go to last post
  8. Closed: Simulating a bi-directional port

    Started by mauromj, 3rd August 2015 20:36
    • Replies: 1
    • Views: 266
    3rd August 2015, 20:59 Go to last post
  9. Closed: dcm and clock issue of fpga

    Started by ornko, 28th July 2015 13:27
    • Replies: 3
    • Views: 556
    3rd August 2015, 16:26 Go to last post
  10. Closed: Is the following legal in VHDL?

    Started by shaiko, 28th July 2015 19:38
    • Replies: 9
    • Views: 570
    3rd August 2015, 14:41 Go to last post
  11. Closed: Simplest programm JHDL Java for Xilinx Artix 7

    Started by junior_hpc, 3rd August 2015 09:57
    • Replies: 1
    • Views: 955
    3rd August 2015, 12:32 Go to last post
  12. Closed: uwire in system verilog

    Started by hulk789, 3rd August 2015 08:40
    • Replies: 1
    • Views: 706
    3rd August 2015, 11:41 Go to last post
  13. [SOLVED]Closed: array fillup problem

    Started by nsgil85, 3rd August 2015 08:45
    • Replies: 1
    • Views: 248
    3rd August 2015, 08:59 Go to last post
  14. Closed: from Matlab workspace data to FPGA xilinx block

    Started by hitx, 29th July 2015 10:38
    • Replies: 5
    • Views: 672
    2nd August 2015, 13:38 Go to last post
  15. Closed: Vhdl code fr matrix inverse

    Started by saran86, 31st July 2015 11:44
    • Replies: 6
    • Views: 806
    31st July 2015, 23:49 Go to last post
  16. [SOLVED]Closed: what is wrong with the following code

    Started by hulk789, 31st July 2015 15:13
    • Replies: 10
    • Views: 546
    31st July 2015, 22:19 Go to last post
  17. [SOLVED]Closed: automatic functions with static storage

    Started by hulk789, 31st July 2015 09:27
    • Replies: 5
    • Views: 519
    31st July 2015, 22:07 Go to last post
  18. [SOLVED]Closed: Artix-7 MIG DDR3 unexpected read/write result and DDR3 address question

    Started by clin684, 12th April 2015 22:17
    • Replies: 7
    • Views: 1,712
    31st July 2015, 20:31 Go to last post
  19. Closed: Bitlib library for VHDL

    Started by Ma Na Ju, 31st July 2015 11:33
    • Replies: 1
    • Views: 614
    31st July 2015, 14:43 Go to last post
  20. Closed: How to declare matrix in verilog

    Started by saran86, 17th July 2015 03:30
    • Replies: 4
    • Views: 872
    31st July 2015, 11:38 Go to last post
  21. Closed: edge and center aligned data

    Started by hulk789, 30th July 2015 05:38
    • Replies: 3
    • Views: 562
    31st July 2015, 07:23 Go to last post
  22. Closed: need verilog/vhdl code for 7-seg display spartan-3 fpga

    Started by ambureddy, 28th July 2015 01:22
    • Replies: 3
    • Views: 776
    30th July 2015, 00:28 Go to last post
  23. Closed: Passing VHDL generics and constants via a tcl script

    Started by matrixofdynamism, 29th July 2015 12:10
    • Replies: 4
    • Views: 962
    29th July 2015, 16:38 Go to last post
  24. Closed: Why do I need on-chip fifo memory core for buffering?

    Started by wannaknow, 28th July 2015 15:37
    • Replies: 5
    • Views: 641
    29th July 2015, 16:20 Go to last post
  25. Closed: SystemVerilog FIFO implementation

    Started by logari84, 28th July 2015 11:05
    • Replies: 6
    • Views: 480
    29th July 2015, 05:54 Go to last post
  26. Closed: sample and hold without latch infered

    Started by hulk789, 28th July 2015 11:21
    • Replies: 5
    • Views: 354
    28th July 2015, 16:54 Go to last post
  27. Closed: RS232 Receiver in VHDL

    Started by omerysmi, 27th July 2015 18:37
    • Replies: 7
    • Views: 1,132
    28th July 2015, 14:41 Go to last post
  28. Closed: efficient parallel real time upsampling

    Started by lgeorge123, 28th July 2015 08:34
    • Replies: 2
    • Views: 268
    28th July 2015, 10:50 Go to last post