1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    93,773
Page 51 of 726 FirstFirst ... 41 49 50 51 52 53 61 101 151 551 ... LastLast
Threads 1501 to 1530 of 21777

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 1
    • Views: 443
    9th November 2015, 01:02 Go to last post
  1. Closed: Req: 802.11a Implementation

    Started by Zerox100, 6th November 2015 16:29
    • Replies: 6
    • Views: 504
    6th November 2015, 22:42 Go to last post
    • Replies: 1
    • Views: 431
    6th November 2015, 16:47 Go to last post
    • Replies: 10
    • Views: 899
    6th November 2015, 01:14 Go to last post
  2. Closed: viterbi 7.0 decoder not generating output data

    Started by Harshit29, 5th November 2015 07:33
    • Replies: 1
    • Views: 358
    5th November 2015, 16:55 Go to last post
  3. [SOLVED]Closed: Seeking help choosing an FPGA develoment board.

    Started by Robo_Pi, 29th October 2015 08:02
    • Replies: 7
    • Views: 726
    5th November 2015, 07:44 Go to last post
  4. Closed: Unsupported Event Control Statement - Verilog HDL

    Started by Valerius, 4th November 2015 18:15
    • Replies: 3
    • Views: 772
    4th November 2015, 19:09 Go to last post
  5. Closed: Combining 2 application c files: NIOS II

    Started by beginner_EDA, 20th October 2015 09:37
    • Replies: 3
    • Views: 447
    4th November 2015, 09:20 Go to last post
  6. Closed: wireless sensor network using fpga

    Started by yashodeepkarne, 4th November 2015 07:49
    • Replies: 0
    • Views: 323
    4th November 2015, 07:49 Go to last post
  7. Closed: Round Robin Arbiter using Verilog HDL

    Started by aravind9, 3rd November 2015 17:53
    • Replies: 5
    • Views: 1,998
    3rd November 2015, 20:16 Go to last post
  8. Closed: conversion from verilog to vhdl

    Started by xiaoanime, 3rd November 2015 08:21
    • Replies: 3
    • Views: 471
    3rd November 2015, 18:55 Go to last post
  9. Closed: DCERPC Packet during UDP transmission in FPGA

    Started by beginner_EDA, 2nd November 2015 10:18
    • Replies: 8
    • Views: 517
    2nd November 2015, 21:55 Go to last post
  10. Closed: always@* vs always@(*)

    Started by harpv, 2nd November 2015 13:57
    • Replies: 1
    • Views: 249
    2nd November 2015, 14:07 Go to last post
  11. Closed: Which wire or reg creates combination loop?

    Started by Kuldeepluvani, 2nd November 2015 02:55
    • Replies: 2
    • Views: 2,290
    2nd November 2015, 05:03 Go to last post
  12. Closed: SDC max skew between lines

    Started by shaiko, 1st November 2015 14:19
    • Replies: 1
    • Views: 576
    2nd November 2015, 00:05 Go to last post
    • Replies: 17
    • Views: 917
    1st November 2015, 17:30 Go to last post
  13. [SOLVED]Closed: Xilinx simulation failed

    Started by sandik93, 31st October 2015 18:17
    • Replies: 4
    • Views: 853
    31st October 2015, 22:30 Go to last post
  14. Closed: Compile Altera Library Files in Questa Through Transcript Question

    Started by Eligineer, 31st October 2015 20:01
    • Replies: 1
    • Views: 471
    31st October 2015, 22:13 Go to last post
  15. Closed: VHDL Time Delay Problem?

    Started by Batur, 30th October 2015 14:37
    • Replies: 4
    • Views: 550
    31st October 2015, 07:11 Go to last post
  16. Closed: Dual Clock FIFO with controlled stream: Verilog

    Started by beginner_EDA, 16th October 2015 13:32
    2 Pages
    1 2
    • Replies: 26
    • Views: 1,850
    31st October 2015, 05:16 Go to last post
  17. Closed: why this block ram vhdl code inffer additional dff?

    Started by milan.km, 30th October 2015 19:35
    • Replies: 4
    • Views: 574
    30th October 2015, 22:54 Go to last post
    • Replies: 4
    • Views: 926
    29th October 2015, 17:24 Go to last post
  18. Closed: How to Translate from Verilog to VHDL

    Started by zwill12, 28th October 2015 20:36
    • Replies: 1
    • Views: 381
    28th October 2015, 20:51 Go to last post
  19. Closed: Why gray counters work?

    Started by shaiko, 28th October 2015 10:18
    • Replies: 8
    • Views: 479
    28th October 2015, 17:32 Go to last post
    • Replies: 2
    • Views: 497
    28th October 2015, 11:38 Go to last post
  20. Closed: understanding the fft output in matlab xilinx system generator

    Started by prashanthi999, 18th October 2015 15:52
    • Replies: 2
    • Views: 597
    27th October 2015, 16:51 Go to last post
    • Replies: 15
    • Views: 1,054
    27th October 2015, 04:08 Go to last post
  21. Closed: use of for loop in vhdl

    Started by jagansai, 22nd October 2015 13:34
    • Replies: 8
    • Views: 725
    27th October 2015, 03:32 Go to last post
  22. Closed: Read data from LPM ROM

    Started by Milenia, 26th October 2015 18:05
    • Replies: 3
    • Views: 472
    26th October 2015, 18:36 Go to last post
  23. Closed: SPI on FPGA - output 1 byte from one port?

    Started by kidi3, 7th October 2015 19:51
    3 Pages
    1 2 3
    • Replies: 58
    • Views: 2,698
    26th October 2015, 15:59 Go to last post