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Threads 1501 to 1530 of 22009

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: HDMI 1.4 1080p@60fps interface Dev board

    Started by nsgil85, 24th February 2016 14:55
    • Replies: 0
    • Views: 355
    24th February 2016, 14:55 Go to last post
  2. [SOLVED]Closed: RGMII connections cross over to achieve a 1:1 Ethernet hub

    Started by dpaul, 22nd February 2016 14:55
    • Replies: 6
    • Views: 860
    24th February 2016, 10:49 Go to last post
  3. Closed: VHDL - purpose of the "group" keyword

    Started by shaiko, 21st February 2016 11:58
    • Replies: 8
    • Views: 644
    23rd February 2016, 11:11 Go to last post
  4. [SOLVED]Closed: Verilog code for 74LS190

    Started by nizdom, 21st February 2016 12:37
    • Replies: 8
    • Views: 886
    22nd February 2016, 15:36 Go to last post
  5. Closed: how to use multiple port declare in systemverilog?

    Started by u24c02, 22nd February 2016 02:32
    • Replies: 0
    • Views: 385
    22nd February 2016, 02:32 Go to last post
  6. Closed: Verilog code statement: #

    Started by kushal nandanwar, 21st February 2016 14:37
    • Replies: 7
    • Views: 502
    21st February 2016, 19:56 Go to last post
  7. Closed: Vivado tcl scripting

    Started by vahidsh, 9th February 2016 17:09
    • Replies: 9
    • Views: 3,157
    21st February 2016, 10:58 Go to last post
  8. Closed: Which VHDL construct is better for clock detection

    Started by garvind25, 18th February 2016 12:12
    • Replies: 6
    • Views: 675
    20th February 2016, 21:42 Go to last post
  9. Closed: YCbCr422 Pixel Data transmit

    Started by nsgil85, 19th February 2016 00:06
    • Replies: 7
    • Views: 825
    20th February 2016, 21:33 Go to last post
    • Replies: 3
    • Views: 838
    19th February 2016, 15:44 Go to last post
  10. Closed: FPGA failed to retrieve data from its EPCQ16

    Started by nsgil85, 7th January 2016 10:05
    • Replies: 2
    • Views: 913
    18th February 2016, 23:51 Go to last post
  11. Closed: occasional power on wrong state of Xilinx virtex II FPGA

    Started by xuexucheng, 14th January 2016 13:16
    2 Pages
    1 2
    • Replies: 21
    • Views: 1,899
    18th February 2016, 16:53 Go to last post
  12. Closed: DSP Slices and IP Block

    Started by bilal_oct, 18th February 2016 14:39
    • Replies: 3
    • Views: 447
    18th February 2016, 16:22 Go to last post
  13. Closed: rtl for clock gating insertion

    Started by sun_ray, 11th February 2016 09:09
    • Replies: 7
    • Views: 1,096
    18th February 2016, 14:10 Go to last post
  14. Closed: Forcing a variable in Modelsim or questasim simulation

    Started by achaleus, 18th February 2016 10:17
    • Replies: 4
    • Views: 2,120
    18th February 2016, 11:17 Go to last post
  15. Closed: Passing Modules as parameters in Verilog ?

    Started by Gpanos, 17th February 2016 18:13
    • Replies: 1
    • Views: 292
    17th February 2016, 18:35 Go to last post
  16. Closed: What is the benefit of using virtual in systemverilog?

    Started by u24c02, 17th February 2016 15:52
    • Replies: 1
    • Views: 373
    17th February 2016, 16:55 Go to last post
  17. Closed: signal depending on a generic

    Started by Binome, 17th February 2016 10:39
    • Replies: 6
    • Views: 433
    17th February 2016, 16:27 Go to last post
  18. Closed: [moved] ZedBoard communication with on-board memory

    Started by bilal_oct, 16th February 2016 15:52
    • Replies: 1
    • Views: 599
    17th February 2016, 09:35 Go to last post
  19. Closed: [moved] telemetry circuit design help requested

    Started by bkelly, 12th February 2016 03:03
    • Replies: 8
    • Views: 1,010
    16th February 2016, 15:31 Go to last post
  20. [SOLVED]Closed: Quartus II synthesis warning

    Started by kasarayv, 16th February 2016 08:27
    • Replies: 3
    • Views: 782
    16th February 2016, 11:17 Go to last post
  21. Closed: which version of ISE support virtex 2 xc2v6000?

    Started by JKR1, 15th February 2016 19:12
    • Replies: 3
    • Views: 456
    16th February 2016, 10:38 Go to last post
  22. Closed: Super confused with LUTs and MUX

    Started by loic88, 14th February 2016 22:25
    • Replies: 9
    • Views: 904
    15th February 2016, 21:51 Go to last post
  23. Closed: PLL or simple clock divider ?

    Started by Binome, 15th February 2016 09:56
    • Replies: 1
    • Views: 580
    15th February 2016, 12:20 Go to last post
  24. Closed: Detecting short pulses

    Started by shaiko, 10th February 2016 20:50
    • Replies: 11
    • Views: 1,007
    13th February 2016, 21:35 Go to last post
  25. Closed: how can we read analog inputs in sparten 3e

    Started by fisat, 13th February 2016 06:38
    • Replies: 2
    • Views: 432
    13th February 2016, 10:55 Go to last post
  26. Closed: VHDL code for Complex matrix multiplication

    Started by saran86, 4th February 2016 05:23
    • Replies: 6
    • Views: 1,263
    11th February 2016, 21:52 Go to last post
  27. Closed: How to implement UART in UTLP

    Started by Shreenivasa, 8th February 2016 11:16
    • Replies: 5
    • Views: 628
    11th February 2016, 18:40 Go to last post
  28. Closed: Full Camera Link Full - Multiple Clocks

    Started by shaiko, 10th February 2016 19:44
    • Replies: 4
    • Views: 564
    11th February 2016, 17:34 Go to last post