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Threads 1501 to 1530 of 21730

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: why this error happened to modelsim?

    Started by JKR1, 17th October 2015 22:17
    • Replies: 1
    • Views: 513
    17th October 2015, 23:12 Go to last post
  2. Closed: Vhdl code for network on chip architecture

    Started by amin_rz, 10th October 2015 19:36
    • Replies: 3
    • Views: 694
    16th October 2015, 15:37 Go to last post
  3. Closed: what is the mechanism used for inter thread communication

    Started by bagavathi, 15th October 2015 12:51
    • Replies: 2
    • Views: 375
    15th October 2015, 20:59 Go to last post
  4. Closed: [Moved]: Write Address Collision

    Started by divya narula, 13th October 2015 19:46
    • Replies: 7
    • Views: 542
    15th October 2015, 16:16 Go to last post
  5. Closed: conversion from vhdl to verilog

    Started by meeraamrita, 15th October 2015 04:43
    • Replies: 1
    • Views: 598
    15th October 2015, 11:27 Go to last post
  6. Closed: Error: Multiple constant drivers

    Started by Hugo17, 14th October 2015 12:21
    • Replies: 5
    • Views: 757
    15th October 2015, 09:32 Go to last post
  7. Closed: Input voltage range for the FPGA

    Started by Vlad., 14th October 2015 07:20
    • Replies: 2
    • Views: 379
    14th October 2015, 07:54 Go to last post
  8. Closed: [moved] xilinx pipeline fft delay

    Started by prashanthi999, 13th October 2015 19:47
    • Replies: 2
    • Views: 586
    14th October 2015, 07:46 Go to last post
  9. Closed: mod 5 counter using jk flip flop

    Started by shalini v, 13th October 2015 08:02
    • Replies: 3
    • Views: 1,145
    13th October 2015, 16:09 Go to last post
  10. Closed: how to show this vector?

    Started by milan.km, 10th October 2015 06:29
    • Replies: 9
    • Views: 528
    13th October 2015, 15:53 Go to last post
  11. Closed: What signals are used to configure a MAX V CPLD?

    Started by matrixofdynamism, 8th October 2015 15:04
    • Replies: 13
    • Views: 877
    13th October 2015, 11:05 Go to last post
  12. [SOLVED]Closed: Problem in deserializing data on xilinx xc7z045-1-fbg676 device

    Started by punit1053, 30th September 2015 19:12
    • Replies: 7
    • Views: 1,037
    12th October 2015, 18:43 Go to last post
    • Replies: 4
    • Views: 509
    12th October 2015, 16:52 Go to last post
    • Replies: 0
    • Views: 565
    12th October 2015, 08:54 Go to last post
  13. Closed: why this error happen?

    Started by JKR1, 11th October 2015 08:20
    • Replies: 3
    • Views: 537
    12th October 2015, 08:24 Go to last post
    • Replies: 3
    • Views: 1,483
    12th October 2015, 04:12 Go to last post
  14. Closed: How to solve this problem about simulation in ISE?

    Started by leda312, 11th October 2015 08:18
    • Replies: 0
    • Views: 354
    11th October 2015, 08:18 Go to last post
  15. Closed: Cant understand ztcam working ! Need some advices

    Started by jenifer0306, 9th October 2015 05:51
    • Replies: 1
    • Views: 463
    9th October 2015, 16:07 Go to last post
  16. Closed: HDL Simulation in Modelsim from Matlab

    Started by rahdirs, 9th October 2015 07:25
    • Replies: 3
    • Views: 618
    9th October 2015, 10:23 Go to last post
  17. Closed: can we implement 8 point fft in matlab simulink?

    Started by sandy3129, 9th October 2015 09:14
    • Replies: 0
    • Views: 340
    9th October 2015, 09:14 Go to last post
  18. [SOLVED]Closed: How to define a VHDL component and package?

    Started by Hugo17, 8th October 2015 12:33
    • Replies: 2
    • Views: 622
    8th October 2015, 15:07 Go to last post
  19. Closed: how to install modelsim on MAC?

    Started by milan.km, 5th October 2015 05:41
    • Replies: 2
    • Views: 1,890
    7th October 2015, 21:09 Go to last post
  20. Closed: 7-Segment 4 Digit display Anode is enabled when 0

    Started by Valerius, 7th October 2015 17:49
    • Replies: 1
    • Views: 568
    7th October 2015, 19:54 Go to last post
  21. Closed: Methods to read the bit file after was burned in to FPGA

    Started by Vlad., 4th August 2015 16:44
    • Replies: 9
    • Views: 977
    7th October 2015, 11:35 Go to last post
  22. [SOLVED]Closed: FIR FIlter Design on FPGA

    Started by keyboardcowboy, 7th October 2015 06:28
    • Replies: 1
    • Views: 511
    7th October 2015, 06:48 Go to last post
  23. [SOLVED]Closed: Problem with Parameters in Verilog

    Started by VuTang, 6th October 2015 08:37
    • Replies: 6
    • Views: 495
    7th October 2015, 03:49 Go to last post
  24. [SOLVED]Closed: always block in testbench, any gotcha?

    Started by legendbb, 6th October 2015 13:39
    • Replies: 2
    • Views: 416
    6th October 2015, 17:02 Go to last post
  25. Closed: WIZ830 module driver in VHDL

    Started by farzaneh_2561, 6th October 2015 15:58
    • Replies: 2
    • Views: 445
    6th October 2015, 16:59 Go to last post
  26. Closed: Bit masking in System Verilog

    Started by degalabalaji1992, 6th October 2015 15:00
    • Replies: 1
    • Views: 1,238
    6th October 2015, 16:53 Go to last post
  27. Closed: Overridden members system verilog classes

    Started by jdshah, 1st October 2015 10:59
    • Replies: 4
    • Views: 659
    6th October 2015, 10:11 Go to last post