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Threads 1501 to 1530 of 21964

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Test vectors for ripemd160 hashing algorithm

    Started by seeker_123, 3rd February 2016 11:00
    • Replies: 8
    • Views: 554
    5th February 2016, 06:27 Go to last post
  2. Closed: common clock for two processors

    Started by Sunayana Chakradhar, 14th January 2016 14:30
    • Replies: 10
    • Views: 771
    4th February 2016, 17:59 Go to last post
  3. Closed: why do we use event control iff in system verilog?

    Started by u24c02, 4th February 2016 09:11
    • Replies: 3
    • Views: 729
    4th February 2016, 11:37 Go to last post
    • Replies: 0
    • Views: 597
    4th February 2016, 03:30 Go to last post
  4. [SOLVED]Closed: MicroBlaze - Can I run an application on Vivado SDK without a board ?

    Started by slutarius, 14th January 2016 07:45
    • Replies: 13
    • Views: 1,675
    3rd February 2016, 20:00 Go to last post
  5. Closed: Help with arcane VHDL errors please in isplever

    Started by business_kid, 1st February 2016 19:30
    • Replies: 7
    • Views: 690
    3rd February 2016, 14:40 Go to last post
    • Replies: 0
    • Views: 503
    3rd February 2016, 11:24 Go to last post
  6. [SOLVED]Closed: Spartan 6 Electrical Characteristics

    Started by tumkayaonur, 1st February 2016 14:47
    • Replies: 3
    • Views: 597
    3rd February 2016, 08:02 Go to last post
  7. [SOLVED]Closed: Can't we use initial statement in interface block in system verilog?

    Started by u24c02, 2nd February 2016 06:22
    • Replies: 3
    • Views: 843
    2nd February 2016, 20:19 Go to last post
  8. Closed: how to use attribute ram_style for entity?

    Started by Port Map, 27th January 2016 06:43
    • Replies: 7
    • Views: 731
    2nd February 2016, 18:22 Go to last post
    • Replies: 3
    • Views: 492
    2nd February 2016, 11:38 Go to last post
  9. Closed: Can we achive get_next_item without TLM Port

    Started by jdshah, 2nd February 2016 08:22
    • Replies: 0
    • Views: 251
    2nd February 2016, 08:22 Go to last post
    • Replies: 1
    • Views: 374
    2nd February 2016, 05:45 Go to last post
    • Replies: 7
    • Views: 622
    1st February 2016, 23:29 Go to last post
  10. Closed: Bubble sortin in System Verilog.

    Started by Johnny_freeman78, 1st February 2016 01:03
    • Replies: 2
    • Views: 831
    1st February 2016, 17:48 Go to last post
  11. Closed: what is the advantage of using 'logic' in systemverilog?

    Started by u24c02, 1st February 2016 05:49
    • Replies: 1
    • Views: 318
    1st February 2016, 17:35 Go to last post
  12. Closed: implementation of 8 bit microcontroller using vhdl

    Started by satyabhagat, 1st February 2016 13:51
    • Replies: 2
    • Views: 444
    1st February 2016, 15:28 Go to last post
  13. [SOLVED]Closed: TCL testbench in Modelsim

    Started by prady019, 16th December 2015 11:08
    • Replies: 16
    • Views: 1,341
    1st February 2016, 15:01 Go to last post
  14. Closed: Regarding PS UART and PL UART difference

    Started by Sunayana Chakradhar, 28th January 2016 09:59
    • Replies: 6
    • Views: 1,239
    1st February 2016, 13:50 Go to last post
  15. Closed: Microblaze migration to new device

    Started by ya_montazar, 30th January 2016 16:12
    • Replies: 4
    • Views: 577
    1st February 2016, 12:57 Go to last post
  16. [SOLVED]Closed: Error while exporting hardware platform for sw dev tools + Vivado 2015.4

    Started by dpaul, 25th January 2016 13:44
    • Replies: 1
    • Views: 3,773
    1st February 2016, 09:34 Go to last post
  17. Closed: Systemverilog - Interface connections

    Started by muhammad_ali, 24th January 2016 14:53
    • Replies: 11
    • Views: 872
    29th January 2016, 17:06 Go to last post
  18. Closed: Using Bitwise XOR or XOR_REDUCE ???

    Started by msdarvishi, 29th January 2016 01:25
    • Replies: 7
    • Views: 765
    29th January 2016, 16:50 Go to last post
  19. Closed: problem in system verilog program

    Started by Ahmed Hisham, 29th January 2016 11:00
    • Replies: 3
    • Views: 484
    29th January 2016, 15:20 Go to last post
  20. Closed: Using an existing xilinx microblaze design on a different FPGA

    Started by fm_com_28, 26th January 2016 19:39
    • Replies: 1
    • Views: 356
    28th January 2016, 14:02 Go to last post
  21. Closed: real time video watermarking using fpga

    Started by plvi, 27th January 2016 06:53
    • Replies: 1
    • Views: 446
    27th January 2016, 08:03 Go to last post
  22. Closed: Xilinx Aurora vs Chip2Chip

    Started by shaiko, 25th January 2016 14:44
    • Replies: 11
    • Views: 1,761
    27th January 2016, 00:43 Go to last post
  23. Closed: Xilinx Remote FPGA bitstream updating

    Started by flote21, 22nd January 2016 12:52
    • Replies: 7
    • Views: 994
    24th January 2016, 19:30 Go to last post
  24. Closed: Looking for Scaler and Interlacer Verilog/VHDL IP

    Started by msulli1, 23rd January 2016 00:33
    • Replies: 0
    • Views: 518
    23rd January 2016, 00:33 Go to last post