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Threads 1501 to 1530 of 22100

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: VHDL - Reading and writing a file to a variable path

    Started by wesleytaylor, 7th April 2016 15:10
    • Replies: 5
    • Views: 1,127
    8th April 2016, 12:54 Go to last post
  2. Closed: Simulink tutorials/ examples for Zynq

    Started by Sunayana Chakradhar, 6th April 2016 05:04
    • Replies: 2
    • Views: 510
    7th April 2016, 08:21 Go to last post
  3. Closed: Simulation problem in 8_bit adder VHDL code

    Started by MSAKARIM, 5th April 2016 20:11
    • Replies: 8
    • Views: 707
    6th April 2016, 16:09 Go to last post
    • Replies: 2
    • Views: 706
    6th April 2016, 13:29 Go to last post
    • Replies: 3
    • Views: 602
    4th April 2016, 23:19 Go to last post
  4. [SOLVED]Closed: Accesing all files in folder using VHDL textio library

    Started by logari84, 30th March 2016 14:11
    • Replies: 4
    • Views: 490
    4th April 2016, 17:31 Go to last post
  5. Closed: calculation of Dynamic Power in Xilinx ISE Design Suite

    Started by niteshtripathi, 31st March 2016 06:25
    • Replies: 1
    • Views: 465
    4th April 2016, 16:29 Go to last post
  6. Closed: Xilinx Virtex 7 memory controller

    Started by shaiko, 31st March 2016 20:55
    • Replies: 6
    • Views: 805
    3rd April 2016, 17:36 Go to last post
  7. Closed: Virtual channel router verilog or vhdl code

    Started by ashish7724, 28th March 2016 11:30
    • Replies: 11
    • Views: 942
    2nd April 2016, 08:23 Go to last post
    • Replies: 0
    • Views: 361
    31st March 2016, 07:12 Go to last post
  8. Closed: A thought about meta-stability

    Started by shaiko, 29th March 2016 17:30
    • Replies: 3
    • Views: 570
    30th March 2016, 16:53 Go to last post
  9. Closed: A simple write transaction for AHB protocol

    Started by sai685, 30th March 2016 10:09
    • Replies: 0
    • Views: 567
    30th March 2016, 10:09 Go to last post
  10. Closed: Interfacing onboard tft lcd of altium nanoboard 3000

    Started by naveenpeterj, 30th March 2016 08:05
    • Replies: 1
    • Views: 530
    30th March 2016, 09:25 Go to last post
  11. Closed: Best way to write VHDL-style functions in SystemVerilog

    Started by vGoodtimes, 26th March 2016 06:18
    • Replies: 6
    • Views: 715
    30th March 2016, 08:59 Go to last post
  12. Closed: [moved] Encoder Decoder on de2 board verilog

    Started by steches, 29th March 2016 16:40
    • Replies: 1
    • Views: 368
    29th March 2016, 16:50 Go to last post
  13. Closed: [moved] Image processing on fpga

    Started by Devanandhan, 29th March 2016 16:21
    • Replies: 1
    • Views: 483
    29th March 2016, 16:28 Go to last post
  14. [SOLVED]Closed: Verilog experimentation but getting too few ports ERROR

    Started by wesleytaylor, 29th March 2016 15:21
    • Replies: 1
    • Views: 467
    29th March 2016, 16:09 Go to last post
  15. Closed: n-vector, m-bits long Counter

    Started by Jaraqui, 27th March 2016 03:51
    • Replies: 4
    • Views: 654
    29th March 2016, 03:41 Go to last post
  16. Closed: Counter in verilog that writes and resets at trigger

    Started by qingcong, 28th March 2016 04:24
    • Replies: 3
    • Views: 596
    28th March 2016, 22:08 Go to last post
  17. Closed: Shift register simulation

    Started by MSAKARIM, 27th March 2016 19:22
    • Replies: 10
    • Views: 688
    28th March 2016, 17:52 Go to last post
  18. Closed: image processing using fpga

    Started by Devanandhan, 26th March 2016 16:02
    • Replies: 1
    • Views: 650
    26th March 2016, 17:06 Go to last post
  19. Closed: How to generate address of a VHDL code on zynq FPGA

    Started by Sunayana Chakradhar, 23rd March 2016 11:07
    • Replies: 9
    • Views: 1,120
    26th March 2016, 09:26 Go to last post
  20. [SOLVED]Closed: Cant fit design in device - error re pins

    Started by preethi19, 23rd March 2016 06:15
    • Replies: 9
    • Views: 1,091
    23rd March 2016, 18:03 Go to last post
  21. [SOLVED]Closed: pin assignments for altera cyclone iii fpga kit

    Started by preethi19, 23rd March 2016 04:06
    • Replies: 2
    • Views: 545
    23rd March 2016, 09:09 Go to last post
  22. Closed: array assignment in vhdl with signed numbers

    Started by 214, 22nd March 2016 07:10
    • Replies: 12
    • Views: 1,077
    22nd March 2016, 18:48 Go to last post
  23. Closed: FSM states coding -> literal representation in waves

    Started by ivlsi, 22nd March 2016 16:36
    • Replies: 1
    • Views: 481
    22nd March 2016, 16:43 Go to last post
  24. Closed: Doubt in xapp1052 reference design from xilinx

    Started by biju4u90, 22nd March 2016 12:03
    • Replies: 3
    • Views: 649
    22nd March 2016, 15:46 Go to last post
  25. Closed: libraries in modelsim in vhdl

    Started by 214, 22nd March 2016 08:09
    • Replies: 4
    • Views: 702
    22nd March 2016, 14:20 Go to last post
  26. Closed: What happens in Synthesis and Implementation

    Started by vimalk, 22nd March 2016 09:46
    • Replies: 1
    • Views: 431
    22nd March 2016, 10:14 Go to last post