1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    98,194
Page 51 of 732 FirstFirst ... 41 49 50 51 52 53 61 101 151 551 ... LastLast
Threads 1501 to 1530 of 21957

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: Spartan 6 Electrical Characteristics

    Started by tumkayaonur, 1st February 2016 14:47
    • Replies: 3
    • Views: 595
    3rd February 2016, 08:02 Go to last post
  2. [SOLVED]Closed: Can't we use initial statement in interface block in system verilog?

    Started by u24c02, 2nd February 2016 06:22
    • Replies: 3
    • Views: 830
    2nd February 2016, 20:19 Go to last post
  3. Closed: how to use attribute ram_style for entity?

    Started by Port Map, 27th January 2016 06:43
    • Replies: 7
    • Views: 717
    2nd February 2016, 18:22 Go to last post
    • Replies: 3
    • Views: 486
    2nd February 2016, 11:38 Go to last post
  4. Closed: Can we achive get_next_item without TLM Port

    Started by jdshah, 2nd February 2016 08:22
    • Replies: 0
    • Views: 249
    2nd February 2016, 08:22 Go to last post
    • Replies: 1
    • Views: 371
    2nd February 2016, 05:45 Go to last post
    • Replies: 7
    • Views: 610
    1st February 2016, 23:29 Go to last post
  5. Closed: Bubble sortin in System Verilog.

    Started by Johnny_freeman78, 1st February 2016 01:03
    • Replies: 2
    • Views: 820
    1st February 2016, 17:48 Go to last post
  6. Closed: what is the advantage of using 'logic' in systemverilog?

    Started by u24c02, 1st February 2016 05:49
    • Replies: 1
    • Views: 314
    1st February 2016, 17:35 Go to last post
  7. Closed: implementation of 8 bit microcontroller using vhdl

    Started by satyabhagat, 1st February 2016 13:51
    • Replies: 2
    • Views: 439
    1st February 2016, 15:28 Go to last post
  8. [SOLVED]Closed: TCL testbench in Modelsim

    Started by prady019, 16th December 2015 11:08
    • Replies: 16
    • Views: 1,323
    1st February 2016, 15:01 Go to last post
  9. Closed: Regarding PS UART and PL UART difference

    Started by Sunayana Chakradhar, 28th January 2016 09:59
    • Replies: 6
    • Views: 1,225
    1st February 2016, 13:50 Go to last post
  10. Closed: Microblaze migration to new device

    Started by ya_montazar, 30th January 2016 16:12
    • Replies: 4
    • Views: 566
    1st February 2016, 12:57 Go to last post
  11. [SOLVED]Closed: Error while exporting hardware platform for sw dev tools + Vivado 2015.4

    Started by dpaul, 25th January 2016 13:44
    • Replies: 1
    • Views: 3,741
    1st February 2016, 09:34 Go to last post
  12. Closed: Systemverilog - Interface connections

    Started by muhammad_ali, 24th January 2016 14:53
    • Replies: 11
    • Views: 856
    29th January 2016, 17:06 Go to last post
  13. Closed: Using Bitwise XOR or XOR_REDUCE ???

    Started by msdarvishi, 29th January 2016 01:25
    • Replies: 7
    • Views: 752
    29th January 2016, 16:50 Go to last post
  14. Closed: problem in system verilog program

    Started by Ahmed Hisham, 29th January 2016 11:00
    • Replies: 3
    • Views: 475
    29th January 2016, 15:20 Go to last post
  15. Closed: Using an existing xilinx microblaze design on a different FPGA

    Started by fm_com_28, 26th January 2016 19:39
    • Replies: 1
    • Views: 348
    28th January 2016, 14:02 Go to last post
  16. Closed: real time video watermarking using fpga

    Started by plvi, 27th January 2016 06:53
    • Replies: 1
    • Views: 440
    27th January 2016, 08:03 Go to last post
  17. Closed: Xilinx Aurora vs Chip2Chip

    Started by shaiko, 25th January 2016 14:44
    • Replies: 11
    • Views: 1,732
    27th January 2016, 00:43 Go to last post
  18. Closed: Xilinx Remote FPGA bitstream updating

    Started by flote21, 22nd January 2016 12:52
    • Replies: 7
    • Views: 984
    24th January 2016, 19:30 Go to last post
  19. Closed: Looking for Scaler and Interlacer Verilog/VHDL IP

    Started by msulli1, 23rd January 2016 00:33
    • Replies: 0
    • Views: 510
    23rd January 2016, 00:33 Go to last post
  20. Closed: Resetting issue in video system using kintex 7 FPGA board

    Started by biju4u90, 19th January 2016 10:14
    • Replies: 5
    • Views: 614
    22nd January 2016, 15:31 Go to last post
  21. Closed: Test bench for multiple frames

    Started by kommu4946, 23rd December 2015 21:47
    • Replies: 7
    • Views: 795
    21st January 2016, 12:54 Go to last post
    • Replies: 3
    • Views: 421
    21st January 2016, 02:52 Go to last post
  22. Closed: frequency divider (430Mhz to 10Mhz)

    Started by navyashree, 13th January 2016 06:52
    • Replies: 5
    • Views: 797
    20th January 2016, 11:13 Go to last post
  23. Closed: Does ISE Design suite works on Linux?

    Started by Morell, 18th January 2016 22:24
    • Replies: 1
    • Views: 483
    18th January 2016, 22:41 Go to last post
  24. [SOLVED]Closed: Help on seed for true random generator in VHDL

    Started by LatticeSemiconductor, 18th January 2016 11:51
    • Replies: 4
    • Views: 1,113
    18th January 2016, 13:57 Go to last post
  25. Closed: Verilog code for module required to design DCO

    Started by niteshtripathi, 17th January 2016 14:48
    • Replies: 1
    • Views: 566
    17th January 2016, 18:23 Go to last post