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Threads 1501 to 1530 of 21881

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: system Verilog code for sigma delta modulator

    Started by abdoo, 18th December 2015 17:37
    • Replies: 3
    • Views: 1,012
    19th December 2015, 23:58 Go to last post
  2. [SOLVED]Closed: IP core to interface parallel asynchronous SRAM with zynq 7020

    Started by Sunayana Chakradhar, 19th December 2015 06:28
    • Replies: 4
    • Views: 868
    19th December 2015, 23:45 Go to last post
  3. [SOLVED]Closed: timing constraints in zynq 7020

    Started by Sunayana Chakradhar, 17th December 2015 06:15
    • Replies: 3
    • Views: 724
    19th December 2015, 13:56 Go to last post
  4. [SOLVED]Closed: Systematic Cyclic Encoder in VHDL

    Started by Morell, 1st December 2015 09:11
    3 Pages
    1 2 3
    • Replies: 44
    • Views: 3,288
    18th December 2015, 17:35 Go to last post
  5. Closed: [moved] Sending 32 bit counter has four 8bit through UART

    Started by Shruthi LS, 18th December 2015 05:47
    • Replies: 4
    • Views: 464
    18th December 2015, 17:20 Go to last post
  6. Closed: VHDL Simulation programs

    Started by MSAKARIM, 18th December 2015 14:05
    • Replies: 2
    • Views: 270
    18th December 2015, 14:30 Go to last post
  7. [SOLVED]Closed: Basic spi timing issues help

    Started by harry998, 12th December 2015 15:51
    • Replies: 4
    • Views: 607
    18th December 2015, 10:35 Go to last post
  8. Closed: XPower Analyzer, dynamic power

    Started by QMA, 16th December 2015 19:16
    • Replies: 3
    • Views: 664
    17th December 2015, 18:26 Go to last post
  9. [SOLVED]Closed: Serial Receiver & transmitter in VHDL

    Started by Morell, 17th December 2015 10:15
    • Replies: 5
    • Views: 623
    17th December 2015, 16:12 Go to last post
  10. Closed: ModelSim "project compileall" how to set include directory

    Started by legendbb, 13th August 2015 19:23
    • Replies: 5
    • Views: 762
    16th December 2015, 08:24 Go to last post
  11. [SOLVED]Closed: how to write a vhdl program with two conditional statements

    Started by prashanthi999, 16th December 2015 03:17
    • Replies: 1
    • Views: 369
    16th December 2015, 07:36 Go to last post
  12. [SOLVED]Closed: Small fast part for tiny design

    Started by business_kid, 14th December 2015 18:00
    • Replies: 6
    • Views: 469
    15th December 2015, 23:44 Go to last post
  13. Closed: Synchronous Clock Domains

    Started by asdf44, 10th December 2015 22:13
    • Replies: 10
    • Views: 703
    15th December 2015, 21:24 Go to last post
  14. Closed: IP address encoding for Memory

    Started by QMA, 14th December 2015 16:40
    • Replies: 13
    • Views: 647
    15th December 2015, 14:41 Go to last post
  15. Closed: I have some questions in the verilog code of 8051 ALU module

    Started by helimpopo, 11th December 2015 08:00
    • Replies: 3
    • Views: 479
    15th December 2015, 01:22 Go to last post
  16. Closed: ADC Verilog Code for Spartan 3E Starter Kit

    Started by prakhars, 27th November 2015 11:33
    • Replies: 5
    • Views: 1,055
    14th December 2015, 20:53 Go to last post
  17. [SOLVED]Closed: Difference between EDK,SDK, vivado and ISE

    Started by Sunayana Chakradhar, 12th December 2015 08:01
    • Replies: 7
    • Views: 2,125
    14th December 2015, 20:40 Go to last post
  18. Closed: FFT Implementation on Altera FPGA

    Started by beginner_EDA, 3rd December 2015 12:26
    • Replies: 13
    • Views: 1,779
    14th December 2015, 16:39 Go to last post
  19. Closed: VHDL error "Cannot read output :" port map error?

    Started by DNA5511, 13th December 2015 22:14
    • Replies: 7
    • Views: 1,107
    14th December 2015, 13:21 Go to last post
  20. Closed: how to create an acknowlegdement signal in vhdl?

    Started by prashanthi999, 11th December 2015 11:51
    • Replies: 1
    • Views: 429
    11th December 2015, 12:16 Go to last post
  21. Closed: Vme bus controller implementation

    Started by Zerox100, 10th December 2015 18:52
    • Replies: 3
    • Views: 520
    11th December 2015, 10:03 Go to last post
  22. Closed: VHDL Possible timing problem?

    Started by sh-eda, 10th December 2015 12:38
    • Replies: 5
    • Views: 610
    11th December 2015, 05:43 Go to last post
    • Replies: 2
    • Views: 1,945
    10th December 2015, 21:31 Go to last post
  23. Closed: Clock uncertainty in FPGA tools

    Started by Dinoc, 9th December 2015 12:53
    • Replies: 4
    • Views: 871
    10th December 2015, 18:18 Go to last post
  24. [SOLVED]Closed: [moved] Can't get data from I2C slave register with FPGA

    Started by tumkayaonur, 25th November 2015 14:20
    3 Pages
    1 2 3
    • Replies: 46
    • Views: 2,597
    10th December 2015, 15:52 Go to last post
  25. Closed: Timing Constraints: OFFSET for bi-directional Port (inout)

    Started by naumanmir, 10th December 2015 08:40
    • Replies: 0
    • Views: 362
    10th December 2015, 08:40 Go to last post
  26. [SOLVED]Closed: FPGA Spartan 6 XC6SLX9 Configuration

    Started by yuhiub90, 7th December 2015 19:08
    • Replies: 11
    • Views: 1,951
    8th December 2015, 20:14 Go to last post
  27. Closed: Calculate overflow flag

    Started by tarjina, 6th December 2015 19:03
    • Replies: 6
    • Views: 855
    8th December 2015, 15:44 Go to last post
  28. Closed: How does march algorithm (rx,...,w/x) detect address decoder fault?

    Started by avelyn94, 7th December 2015 10:49
    • Replies: 2
    • Views: 393
    8th December 2015, 06:17 Go to last post
  29. Closed: Delayed assign in Verilog

    Started by shaiko, 7th December 2015 12:58
    • Replies: 9
    • Views: 1,531
    7th December 2015, 18:07 Go to last post