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Threads 1501 to 1530 of 22001

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Which VHDL construct is better for clock detection

    Started by garvind25, 18th February 2016 12:12
    • Replies: 6
    • Views: 672
    20th February 2016, 21:42 Go to last post
  2. Closed: YCbCr422 Pixel Data transmit

    Started by nsgil85, 19th February 2016 00:06
    • Replies: 7
    • Views: 817
    20th February 2016, 21:33 Go to last post
    • Replies: 3
    • Views: 836
    19th February 2016, 15:44 Go to last post
  3. Closed: FPGA failed to retrieve data from its EPCQ16

    Started by nsgil85, 7th January 2016 10:05
    • Replies: 2
    • Views: 908
    18th February 2016, 23:51 Go to last post
  4. Closed: occasional power on wrong state of Xilinx virtex II FPGA

    Started by xuexucheng, 14th January 2016 13:16
    2 Pages
    1 2
    • Replies: 21
    • Views: 1,890
    18th February 2016, 16:53 Go to last post
  5. Closed: DSP Slices and IP Block

    Started by bilal_oct, 18th February 2016 14:39
    • Replies: 3
    • Views: 446
    18th February 2016, 16:22 Go to last post
  6. Closed: rtl for clock gating insertion

    Started by sun_ray, 11th February 2016 09:09
    • Replies: 7
    • Views: 1,090
    18th February 2016, 14:10 Go to last post
  7. Closed: Forcing a variable in Modelsim or questasim simulation

    Started by achaleus, 18th February 2016 10:17
    • Replies: 4
    • Views: 2,101
    18th February 2016, 11:17 Go to last post
  8. Closed: Passing Modules as parameters in Verilog ?

    Started by Gpanos, 17th February 2016 18:13
    • Replies: 1
    • Views: 290
    17th February 2016, 18:35 Go to last post
  9. Closed: What is the benefit of using virtual in systemverilog?

    Started by u24c02, 17th February 2016 15:52
    • Replies: 1
    • Views: 371
    17th February 2016, 16:55 Go to last post
  10. Closed: signal depending on a generic

    Started by Binome, 17th February 2016 10:39
    • Replies: 6
    • Views: 430
    17th February 2016, 16:27 Go to last post
  11. Closed: [moved] ZedBoard communication with on-board memory

    Started by bilal_oct, 16th February 2016 15:52
    • Replies: 1
    • Views: 596
    17th February 2016, 09:35 Go to last post
  12. Closed: [moved] telemetry circuit design help requested

    Started by bkelly, 12th February 2016 03:03
    • Replies: 8
    • Views: 1,009
    16th February 2016, 15:31 Go to last post
  13. [SOLVED]Closed: Quartus II synthesis warning

    Started by kasarayv, 16th February 2016 08:27
    • Replies: 3
    • Views: 775
    16th February 2016, 11:17 Go to last post
  14. Closed: which version of ISE support virtex 2 xc2v6000?

    Started by JKR1, 15th February 2016 19:12
    • Replies: 3
    • Views: 451
    16th February 2016, 10:38 Go to last post
  15. Closed: Super confused with LUTs and MUX

    Started by loic88, 14th February 2016 22:25
    • Replies: 9
    • Views: 896
    15th February 2016, 21:51 Go to last post
  16. Closed: PLL or simple clock divider ?

    Started by Binome, 15th February 2016 09:56
    • Replies: 1
    • Views: 577
    15th February 2016, 12:20 Go to last post
  17. Closed: Detecting short pulses

    Started by shaiko, 10th February 2016 20:50
    • Replies: 11
    • Views: 1,004
    13th February 2016, 21:35 Go to last post
  18. Closed: how can we read analog inputs in sparten 3e

    Started by fisat, 13th February 2016 06:38
    • Replies: 2
    • Views: 429
    13th February 2016, 10:55 Go to last post
  19. Closed: VHDL code for Complex matrix multiplication

    Started by saran86, 4th February 2016 05:23
    • Replies: 6
    • Views: 1,257
    11th February 2016, 21:52 Go to last post
  20. Closed: How to implement UART in UTLP

    Started by Shreenivasa, 8th February 2016 11:16
    • Replies: 5
    • Views: 625
    11th February 2016, 18:40 Go to last post
  21. Closed: Full Camera Link Full - Multiple Clocks

    Started by shaiko, 10th February 2016 19:44
    • Replies: 4
    • Views: 561
    11th February 2016, 17:34 Go to last post
  22. Closed: need help regarding interfacing ADC 0804 or ADC 0808 with papilio one

    Started by fisat, 10th February 2016 07:59
    • Replies: 2
    • Views: 547
    10th February 2016, 17:17 Go to last post
    • Replies: 6
    • Views: 1,110
    10th February 2016, 16:58 Go to last post
  23. Closed: Dual FPGA file programming

    Started by nsgil85, 4th February 2016 18:30
    • Replies: 4
    • Views: 744
    10th February 2016, 10:37 Go to last post
  24. Closed: need Verilog program for Datapath Circuit show below

    Started by musclemania05, 9th February 2016 06:33
    • Replies: 8
    • Views: 713
    9th February 2016, 21:52 Go to last post
  25. Closed: Is it possible using ChipScope for a very high frequency clock?

    Started by msdarvishi, 8th February 2016 23:03
    • Replies: 7
    • Views: 744
    9th February 2016, 21:48 Go to last post
  26. Closed: ISSUES WITH ALTERA CUSTOM PHY 10GBITS - Alignment

    Started by Eligineer, 9th February 2016 19:28
    • Replies: 0
    • Views: 457
    9th February 2016, 19:28 Go to last post
  27. Closed: What is HSSI_PMA_AUX?

    Started by nervecell_23, 9th February 2016 19:20
    • Replies: 0
    • Views: 318
    9th February 2016, 19:20 Go to last post
  28. [SOLVED]Closed: fanout problem while compiling vhdl code in libera software

    Started by Nithyaselvaraj, 9th February 2016 14:19
    • Replies: 1
    • Views: 330
    9th February 2016, 14:45 Go to last post