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Threads 15031 to 15060 of 21959

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Which parameter decides on the size of a bit file?

    Started by amitgangwar_vlsi, 16th April 2008 07:18
    • Replies: 4
    • Views: 1,789
    18th April 2008, 05:24 Go to last post
    • Replies: 8
    • Views: 2,750
    18th April 2008, 03:02 Go to last post
  2. Closed: request free FPGA kit for development?

    Started by nicklas_a74, 17th April 2008 18:35
    • Replies: 1
    • Views: 2,137
    18th April 2008, 00:07 Go to last post
  3. Closed: how to test usb mass storage transfer speed ?

    Started by shield, 11th April 2008 16:21
    • Replies: 2
    • Views: 1,343
    17th April 2008, 16:34 Go to last post
  4. Closed: What is the VHDL code for a PI and PD controller?

    Started by microguy, 17th April 2008 14:58
    • Replies: 0
    • Views: 808
    17th April 2008, 14:58 Go to last post
  5. Closed: This FF/Latch will be trimmed during the optimization proces

    Started by State, 16th April 2008 20:05
    • Replies: 1
    • Views: 1,030
    17th April 2008, 13:09 Go to last post
  6. Closed: Materials to learn about the basics of FPGA

    Started by galuison_20, 17th April 2008 11:39
    • Replies: 1
    • Views: 752
    17th April 2008, 12:35 Go to last post
  7. Closed: i want some codes about cooperative communication

    Started by lovemoon, 17th April 2008 08:08
    • Replies: 0
    • Views: 764
    17th April 2008, 08:08 Go to last post
  8. Closed: 2-Point DFT implemetation in Hardware

    Started by kalyansrinivas, 17th April 2008 07:33
    • Replies: 0
    • Views: 683
    17th April 2008, 07:33 Go to last post
  9. Closed: Using DDR SDRAM module as video memory (XUPV2P)

    Started by BlackOps, 14th April 2008 18:31
    • Replies: 3
    • Views: 2,973
    16th April 2008, 11:55 Go to last post
  10. Closed: strange Timing result of Array multiplier.....how?

    Started by amitjagtap, 16th April 2008 10:52
    • Replies: 0
    • Views: 958
    16th April 2008, 10:52 Go to last post
  11. Closed: What is the best software for VHDL?

    Started by leo111, 24th May 2006 10:39
    2 Pages
    1 2
    • Replies: 38
    • Views: 3,895
    16th April 2008, 09:52 Go to last post
  12. Closed: verilog(clock problem)------urgent

    Started by deeptijohar, 1st April 2008 11:51
    • Replies: 4
    • Views: 732
    16th April 2008, 09:06 Go to last post
  13. Closed: Mentor Graphics Catapult C Synthesis

    Started by antoon, 15th April 2008 13:06
    • Replies: 1
    • Views: 1,214
    16th April 2008, 08:52 Go to last post
  14. Closed: Information about USB packet formats

    Started by prithvivlsi, 16th April 2008 08:50
    • Replies: 0
    • Views: 742
    16th April 2008, 08:50 Go to last post
  15. Closed: Integrating HDL modules and CoreGenerator parts using EDK

    Started by Rob B, 20th March 2008 14:02
    • Replies: 12
    • Views: 4,448
    16th April 2008, 05:35 Go to last post
  16. Closed: Wrong output while trying to use module repeatedly..Help!

    Started by deepavlsi, 4th April 2008 15:14
    • Replies: 3
    • Views: 940
    15th April 2008, 16:40 Go to last post
  17. Closed: how to enable the pull up resistor in Quartus2 using cpld

    Started by pwq1999, 15th April 2008 06:07
    • Replies: 4
    • Views: 9,182
    15th April 2008, 15:56 Go to last post
  18. Closed: Doubts related to timing delay

    Started by deepu_s_s, 15th April 2008 12:23
    • Replies: 1
    • Views: 665
    15th April 2008, 13:11 Go to last post
  19. Closed: DDR controller MIG and XPS

    Started by LatDrIvE, 15th April 2008 08:01
    • Replies: 2
    • Views: 1,291
    15th April 2008, 09:08 Go to last post
  20. Closed: Using DDR SDRAM as video memory

    Started by BlackOps, 14th April 2008 18:28
    • Replies: 0
    • Views: 768
    14th April 2008, 18:28 Go to last post
  21. Closed: about $fopen,$fgetc,$fputc

    Started by sagar_saga01, 11th April 2008 06:15
    • Replies: 3
    • Views: 3,909
    14th April 2008, 08:36 Go to last post
  22. Closed: The difference between the FPGA and development board

    Started by deepu_s_s, 13th April 2008 05:58
    • Replies: 5
    • Views: 1,079
    14th April 2008, 06:38 Go to last post
  23. Closed: Help me with designing a modular exponential unit for a thesis

    Started by moharaza, 12th April 2008 21:24
    • Replies: 16
    • Views: 1,257
    13th April 2008, 21:40 Go to last post
  24. Closed: Looking for FFT core with FSL connectivity

    Started by Rob B, 13th April 2008 20:08
    • Replies: 0
    • Views: 708
    13th April 2008, 20:08 Go to last post
  25. Closed: How to convert 'real' values to std_logic_vector ?

    Started by GeekWizard, 6th April 2008 23:22
    • Replies: 8
    • Views: 62,534
    13th April 2008, 18:45 Go to last post
  26. Closed: How do we programm CPLDs ( PROM )

    Started by gbaerf, 11th April 2008 13:54
    • Replies: 3
    • Views: 939
    13th April 2008, 18:17 Go to last post
  27. Closed: XUPV2P and DDR memory modules

    Started by BlackOps, 2nd April 2008 11:35
    • Replies: 6
    • Views: 2,472
    13th April 2008, 12:20 Go to last post
  28. Closed: What does memory inference mean ?

    Started by State, 11th April 2008 19:25
    • Replies: 3
    • Views: 3,032
    12th April 2008, 20:08 Go to last post
  29. Closed: When should we use bit and when std_logic in VHDL?

    Started by deepu_s_s, 12th April 2008 11:54
    • Replies: 4
    • Views: 1,432
    12th April 2008, 18:41 Go to last post