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Threads 15031 to 15060 of 21842

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: What are the methods for SSB?

    Started by nktu, 1st March 2008 10:40
    • Replies: 3
    • Views: 914
    2nd April 2008, 07:29 Go to last post
  2. Closed: web_sever problem,thanks

    Started by 8a112, 1st April 2008 05:57
    • Replies: 1
    • Views: 1,060
    2nd April 2008, 05:00 Go to last post
  3. Closed: Help me design the H.264 codec

    Started by deepu_s_s, 27th March 2008 12:15
    • Replies: 11
    • Views: 1,024
    2nd April 2008, 04:12 Go to last post
  4. Closed: S3E starter kit , jtag programming question ...

    Started by hm_fa_da, 1st April 2008 15:06
    • Replies: 1
    • Views: 1,090
    1st April 2008, 21:39 Go to last post
  5. Closed: IO on Z80 SoC - Buffer it or not to Buffer it ?

    Started by RRRED, 26th March 2008 12:59
    • Replies: 1
    • Views: 1,528
    1st April 2008, 21:09 Go to last post
  6. Closed: did any one knows how to place the spare cells in Encounter

    Started by youmoros, 1st April 2008 21:01
    • Replies: 0
    • Views: 887
    1st April 2008, 21:01 Go to last post
  7. Closed: PLL & FPGA design

    Started by zarizi, 5th December 2004 11:30
    • Replies: 13
    • Views: 5,603
    1st April 2008, 20:56 Go to last post
  8. Closed: ncsim waveform editor

    Started by sharada.144, 1st April 2008 12:37
    • Replies: 2
    • Views: 2,319
    1st April 2008, 14:33 Go to last post
  9. Closed: sysnthesis report help...

    Started by abhi_459, 1st April 2008 07:33
    • Replies: 1
    • Views: 662
    1st April 2008, 13:55 Go to last post
  10. Closed: How to implement baud rate generator?

    Started by research_vlsi, 21st December 2006 10:54
    • Replies: 2
    • Views: 3,466
    1st April 2008, 13:46 Go to last post
  11. Closed: Looking for specifications and block diagram of USART

    Started by jrajvlsi, 9th November 2006 10:57
    • Replies: 2
    • Views: 1,441
    1st April 2008, 13:36 Go to last post
  12. Closed: Multiple clock domain sync

    Started by vintujose, 26th March 2008 06:42
    • Replies: 5
    • Views: 3,681
    1st April 2008, 07:23 Go to last post
    • Replies: 7
    • Views: 15,521
    1st April 2008, 07:08 Go to last post
  13. Closed: How to Convert from "STD_LOGIC_VECTOR to STD_LOGIC"

    Started by xtcx, 24th March 2008 15:46
    • Replies: 11
    • Views: 30,064
    1st April 2008, 07:02 Go to last post
  14. Closed: Help me capture video output from a camera using FPGA

    Started by madmaiden, 26th March 2008 22:39
    • Replies: 3
    • Views: 1,418
    1st April 2008, 01:42 Go to last post
  15. Closed: How to convert PAL to VGA?

    Started by cell1, 24th March 2008 07:07
    • Replies: 11
    • Views: 5,917
    31st March 2008, 11:44 Go to last post
  16. Closed: hardware interface and a hardware controller

    Started by MFM, 31st March 2008 09:27
    • Replies: 1
    • Views: 877
    31st March 2008, 11:36 Go to last post
  17. Closed: PS2 Keyboard with Spartan 3E

    Started by drifterz, 30th March 2008 17:09
    • Replies: 1
    • Views: 6,470
    31st March 2008, 10:34 Go to last post
  18. Closed: about two clks and sampling timing

    Started by meisuo_1985312, 31st March 2008 07:05
    • Replies: 0
    • Views: 564
    31st March 2008, 07:05 Go to last post
  19. Closed: warning of output pins stuck at gnd or vcc (CPLD)

    Started by McMurry, 29th March 2008 18:59
    • Replies: 10
    • Views: 6,288
    31st March 2008, 00:13 Go to last post
  20. Closed: Number theory and FPGAs

    Started by 555lin, 17th March 2008 14:46
    • Replies: 2
    • Views: 780
    30th March 2008, 16:12 Go to last post
  21. Closed: which FPGA kit is best for beginners?

    Started by Mr.Good, 20th March 2008 00:32
    • Replies: 6
    • Views: 4,340
    30th March 2008, 15:24 Go to last post
    • Replies: 4
    • Views: 769
    30th March 2008, 15:07 Go to last post
  22. Closed: Delay issue-----urgent

    Started by deeptijohar, 20th March 2008 05:33
    • Replies: 5
    • Views: 853
    29th March 2008, 11:13 Go to last post
  23. Closed: Looking for information about RSG algorithm

    Started by money_kandan2004, 28th February 2008 09:12
    • Replies: 2
    • Views: 785
    29th March 2008, 10:24 Go to last post
  24. Closed: Check my math on this memory size problem

    Started by andrew257, 27th March 2008 20:57
    • Replies: 2
    • Views: 580
    29th March 2008, 07:15 Go to last post
  25. Closed: swapp the four values in vhdl

    Started by swapnil_vlsi, 20th March 2008 05:46
    • Replies: 3
    • Views: 935
    29th March 2008, 06:47 Go to last post
  26. Closed: Post Placement & Route Simulation in (Cadence)NC Launch

    Started by Mirzaaur, 28th March 2008 18:51
    • Replies: 0
    • Views: 743
    28th March 2008, 18:51 Go to last post
  27. Closed: why Xilinx doesn't support Dual-Rank DIMM

    Started by adamsogood, 27th March 2008 14:09
    • Replies: 3
    • Views: 1,369
    28th March 2008, 14:39 Go to last post
  28. Closed: need the Schematic for SPartan3A DSP-3400A starter kit

    Started by madu2023, 28th March 2008 05:44
    • Replies: 2
    • Views: 1,125
    28th March 2008, 07:46 Go to last post