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Threads 15001 to 15030 of 21555

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: No Output from VHDL code !?

    Started by GeekWizard, 19th February 2008 17:58
    • Replies: 2
    • Views: 717
    19th February 2008, 19:51 Go to last post
  2. Closed: How to select FPGA chip for baseband modem?

    Started by fryFox, 17th February 2008 03:00
    • Replies: 3
    • Views: 1,002
    19th February 2008, 16:15 Go to last post
  3. Closed: Embedding an ARM soft core to Actel Proasic 3

    Started by bjzhangwn, 11th December 2005 10:24
    • Replies: 6
    • Views: 1,291
    19th February 2008, 13:28 Go to last post
  4. Closed: Looking for xilinx MGT training material

    Started by cawan, 7th December 2004 06:43
    • Replies: 4
    • Views: 1,878
    19th February 2008, 12:05 Go to last post
  5. Closed: Modelsim error : bad pointer access

    Started by thabet, 18th February 2008 18:31
    • Replies: 1
    • Views: 2,871
    19th February 2008, 09:47 Go to last post
  6. Closed: doubt in I2C address comparator

    Started by deepu_s_s, 13th February 2008 17:19
    • Replies: 2
    • Views: 738
    19th February 2008, 08:46 Go to last post
  7. Closed: Estimation of power consumption using Xpower tool

    Started by rz56, 16th February 2008 19:34
    • Replies: 2
    • Views: 828
    18th February 2008, 16:38 Go to last post
  8. Closed: need help implement 16 bit carry select adder

    Started by nearownkira, 18th February 2008 05:03
    • Replies: 2
    • Views: 2,027
    18th February 2008, 16:38 Go to last post
  9. Closed: VHDL design how to keep a dynamic register data as constant?

    Started by EDA_hg81, 18th February 2008 05:02
    • Replies: 1
    • Views: 957
    18th February 2008, 15:19 Go to last post
  10. Closed: BRAM detected as Others option

    Started by platopathrose, 18th February 2008 13:56
    • Replies: 2
    • Views: 747
    18th February 2008, 15:10 Go to last post
  11. Closed: Help for implementing parallel adder

    Started by platopathrose, 15th February 2008 05:08
    • Replies: 3
    • Views: 1,078
    18th February 2008, 13:59 Go to last post
    • Replies: 5
    • Views: 1,132
    18th February 2008, 13:34 Go to last post
  12. Closed: ARM7TDMI Core Chip request!

    Started by cfriend, 25th July 2006 07:53
    • Replies: 11
    • Views: 1,916
    18th February 2008, 10:49 Go to last post
  13. Closed: PLD's how fast, big strong durable......How to digital?

    Started by wafer101, 30th August 2006 02:37
    • Replies: 1
    • Views: 860
    18th February 2008, 10:46 Go to last post
  14. Closed: Unexpected token error in a code

    Started by andrew257, 16th February 2008 21:02
    • Replies: 3
    • Views: 1,683
    17th February 2008, 11:29 Go to last post
  15. Closed: Memory: Small problem

    Started by sameem_shabbir, 16th February 2008 04:15
    • Replies: 3
    • Views: 781
    16th February 2008, 20:43 Go to last post
  16. Closed: Looking for some beginner materials about FPGA

    Started by gharibe_12000, 15th February 2008 14:18
    • Replies: 5
    • Views: 1,185
    16th February 2008, 20:12 Go to last post
  17. Closed: How to set up PULL UP resistor in Spratn 3?

    Started by EDA_hg81, 15th February 2008 01:43
    • Replies: 6
    • Views: 1,764
    16th February 2008, 19:51 Go to last post
  18. Closed: HOW TO CORRECT THIS ERROR

    Started by simu, 15th February 2008 11:37
    • Replies: 3
    • Views: 1,227
    15th February 2008, 23:43 Go to last post
  19. Closed: [Req] Virtex 4 & MCU (AVR or ARM) interface

    Started by elsalvador, 15th February 2008 12:18
    • Replies: 1
    • Views: 939
    15th February 2008, 19:42 Go to last post
  20. Closed: How to give 4 sequences 127 points each with point holding 4 bits?

    Started by neefa, 15th February 2008 05:11
    • Replies: 1
    • Views: 712
    15th February 2008, 16:40 Go to last post
  21. Closed: IOBs in Spartan 2 exceeded

    Started by Nikolai, 13th February 2008 15:36
    • Replies: 10
    • Views: 1,112
    15th February 2008, 15:16 Go to last post
  22. Closed: help with verilog project topic

    Started by vineethn, 15th February 2008 07:41
    • Replies: 1
    • Views: 780
    15th February 2008, 14:09 Go to last post
  23. Closed: Solution to delaying the signal in VHDL code

    Started by koce, 10th January 2008 11:34
    • Replies: 12
    • Views: 3,883
    15th February 2008, 07:03 Go to last post
  24. Closed: How to convert Sinewave to sqr wave from ADC samples?

    Started by xtcx, 12th February 2008 14:55
    • Replies: 12
    • Views: 7,211
    15th February 2008, 06:51 Go to last post
  25. Closed: How to read/write DDR Memory in Microblaze ?

    Started by BuBEE, 14th February 2008 18:47
    • Replies: 1
    • Views: 2,335
    14th February 2008, 20:18 Go to last post
  26. Closed: how to specifiy range for string datatype in VHDL

    Started by venkatesankalidass, 22nd January 2008 16:00
    • Replies: 3
    • Views: 1,136
    14th February 2008, 14:04 Go to last post
  27. Closed: Why we have 9 values in Std_logic?

    Started by gck, 14th February 2008 05:37
    • Replies: 1
    • Views: 674
    14th February 2008, 13:20 Go to last post
  28. Closed: Looking for basic docs on System Verilog

    Started by vinodkumar, 25th January 2008 13:22
    • Replies: 1
    • Views: 1,014
    14th February 2008, 11:39 Go to last post
  29. Closed: Cyclone III starter board

    Started by fastian1o1, 14th February 2008 07:10
    • Replies: 0
    • Views: 997
    14th February 2008, 07:10 Go to last post