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Threads 15001 to 15030 of 21730

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: FPGA for DSP coprocessing duties, addr/data bus...

    Started by vandelay, 17th March 2008 06:10
    • Replies: 0
    • Views: 900
    17th March 2008, 06:10 Go to last post
  2. Closed: 22v10 programmer needed...!!!

    Started by hussain_kiet, 14th March 2008 06:48
    • Replies: 4
    • Views: 3,945
    17th March 2008, 05:05 Go to last post
  3. Closed: EDK and GDB - Code does not run

    Started by Rob B, 13th March 2008 16:55
    • Replies: 6
    • Views: 1,439
    16th March 2008, 18:18 Go to last post
  4. Closed: Help me edit m file code for the black box

    Started by r_a_c_a_4_u, 16th March 2008 16:19
    • Replies: 0
    • Views: 724
    16th March 2008, 16:19 Go to last post
  5. Closed: I want phase shift in DDS output depending upon the input

    Started by r_a_c_a_4_u, 16th March 2008 06:18
    • Replies: 2
    • Views: 1,197
    16th March 2008, 15:21 Go to last post
  6. Closed: Chipscope analyzer problem with buffered data

    Started by ehsan_iut, 13th March 2008 16:42
    • Replies: 5
    • Views: 1,084
    16th March 2008, 13:26 Go to last post
  7. Closed: How to implement y=sinx in VHDL?

    Started by sachinmaheshwari, 13th March 2008 13:15
    • Replies: 13
    • Views: 2,940
    16th March 2008, 12:50 Go to last post
  8. Closed: hardware speed vs software speed

    Started by anandanips, 13th March 2008 08:28
    • Replies: 8
    • Views: 1,854
    16th March 2008, 09:01 Go to last post
  9. Closed: How to do place and route in SOC Encounter

    Started by sachinmaheshwari, 15th March 2008 19:18
    • Replies: 0
    • Views: 721
    15th March 2008, 19:18 Go to last post
  10. Closed: frequency multiplier on fpga

    Started by rave1786, 9th March 2008 19:50
    • Replies: 4
    • Views: 2,559
    15th March 2008, 17:31 Go to last post
  11. Closed: delay in timesim simulation in Modelsim

    Started by gck, 14th March 2008 06:40
    • Replies: 3
    • Views: 1,238
    15th March 2008, 17:05 Go to last post
  12. Closed: not able to generate sine wave using DDS in simulink

    Started by r_a_c_a_4_u, 14th March 2008 13:36
    • Replies: 1
    • Views: 3,051
    15th March 2008, 12:27 Go to last post
  13. Closed: problem about coregen

    Started by taolibuyan, 13th December 2007 15:06
    • Replies: 3
    • Views: 1,747
    15th March 2008, 08:35 Go to last post
  14. Closed: How to implement Divisio Function on Xilinix V4 ?

    Started by omara007, 15th March 2008 02:11
    • Replies: 1
    • Views: 688
    15th March 2008, 08:21 Go to last post
    • Replies: 0
    • Views: 1,033
    15th March 2008, 07:39 Go to last post
  15. Closed: need XCV100e-8pq240 datasheet

    Started by amburose, 14th March 2008 07:30
    • Replies: 5
    • Views: 696
    14th March 2008, 18:13 Go to last post
  16. Closed: Flat Panel Evaluation Platform

    Started by ep20k, 14th January 2008 11:46
    • Replies: 7
    • Views: 2,140
    14th March 2008, 17:53 Go to last post
  17. Closed: Verilog code for correlation of two images

    Started by sameem_shabbir, 8th February 2008 17:08
    • Replies: 16
    • Views: 2,698
    14th March 2008, 08:31 Go to last post
  18. Closed: The reason and solution for XST ERROR 1534

    Started by BlackOps, 12th March 2008 19:25
    • Replies: 4
    • Views: 6,255
    14th March 2008, 08:19 Go to last post
  19. Closed: Implement sar control in pld , need example ???

    Started by wls, 15th June 2007 00:56
    • Replies: 2
    • Views: 1,160
    14th March 2008, 01:50 Go to last post
  20. Closed: multi target tracking

    Started by priyamani, 19th February 2008 08:45
    • Replies: 12
    • Views: 3,590
    13th March 2008, 20:29 Go to last post
  21. Closed: VHDL: Truncate signed to std_logic_vector

    Started by clsfox, 13th March 2008 12:11
    • Replies: 4
    • Views: 5,808
    13th March 2008, 19:41 Go to last post
  22. Closed: Implementing a multiplier with 4 inputs and 2 outputs.

    Started by neefa, 5th March 2008 11:32
    • Replies: 8
    • Views: 1,139
    13th March 2008, 19:36 Go to last post
  23. Closed: How can I do the best in programming VHDL !?

    Started by kangta, 4th April 2006 03:22
    • Replies: 13
    • Views: 2,591
    13th March 2008, 14:14 Go to last post
  24. Closed: Post -synthesis simulation

    Started by kalyansrinivas, 7th March 2008 07:33
    • Replies: 6
    • Views: 6,632
    13th March 2008, 11:53 Go to last post
  25. Closed: Advice Request-PLC Siemens S-400

    Started by zare.v, 12th March 2008 23:13
    • Replies: 0
    • Views: 1,209
    12th March 2008, 23:13 Go to last post
  26. Closed: Looking for VHDL code for receiver UART

    Started by Elexstudent, 3rd April 2007 05:25
    • Replies: 5
    • Views: 3,974
    12th March 2008, 19:08 Go to last post
  27. Closed: Instantiatiion of Altera Ip cores?

    Started by irshan, 14th February 2008 05:47
    • Replies: 2
    • Views: 1,099
    12th March 2008, 17:42 Go to last post
  28. Closed: Books to start learning EDK programming

    Started by rajaselvamj, 6th March 2008 09:13
    • Replies: 6
    • Views: 1,203
    12th March 2008, 11:44 Go to last post
  29. Closed: VHDL interview questions

    Started by bcdeepak, 8th July 2007 11:27
    • Replies: 2
    • Views: 9,176
    12th March 2008, 11:02 Go to last post