1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    95,068
Page 501 of 728 FirstFirst ... 401 451 491 499 500 501 502 503 511 551 601 ... LastLast
Threads 15001 to 15030 of 21840

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: VHDL if statement enquiry

    Started by drifterz, 5th April 2008 11:40
    • Replies: 5
    • Views: 3,375
    5th April 2008, 20:55 Go to last post
  2. Closed: how to read hex file by VHDL

    Started by shenql, 5th April 2008 04:42
    • Replies: 6
    • Views: 10,734
    5th April 2008, 20:50 Go to last post
  3. Closed: How can i read a text file inut in verilog

    Started by sagar_saga01, 5th April 2008 12:19
    • Replies: 1
    • Views: 1,384
    5th April 2008, 17:37 Go to last post
  4. Closed: Error: Node instance "u1" instantiates undefined

    Started by YeeDeeAii, 3rd April 2008 14:03
    • Replies: 3
    • Views: 7,311
    5th April 2008, 01:05 Go to last post
  5. Closed: Synthesis Error in code to find power,and modulus...Help

    Started by deepavlsi, 3rd April 2008 18:49
    • Replies: 5
    • Views: 1,210
    4th April 2008, 21:23 Go to last post
  6. Closed: displaying text on screen by FPGA

    Started by salma ali bakr, 4th April 2008 19:05
    • Replies: 4
    • Views: 2,167
    4th April 2008, 21:17 Go to last post
  7. Closed: role of static timing analysis tools in Design process

    Started by ar_m_in, 4th October 2007 16:24
    • Replies: 6
    • Views: 1,309
    4th April 2008, 19:02 Go to last post
  8. Closed: ispLEVER Classic problem

    Started by ITP, 4th April 2008 09:34
    • Replies: 1
    • Views: 2,388
    4th April 2008, 17:11 Go to last post
  9. Closed: verilog equivalent of C code acc=acc+out;

    Started by neefa, 4th April 2008 10:45
    • Replies: 1
    • Views: 851
    4th April 2008, 11:42 Go to last post
  10. Closed: coarse grain test benchs for FPGAs

    Started by saint202, 3rd April 2008 16:08
    • Replies: 3
    • Views: 611
    4th April 2008, 11:34 Go to last post
  11. Closed: multiplication of twiddle factor using cordic algorithm

    Started by vash77, 3rd April 2008 19:16
    • Replies: 2
    • Views: 1,880
    4th April 2008, 05:48 Go to last post
  12. Closed: How to read MP3 files on SD card ?( DE2 board mp4 player project)

    Started by nindra, 28th March 2008 10:44
    • Replies: 4
    • Views: 5,469
    4th April 2008, 04:25 Go to last post
  13. Closed: Is there any journal that refrences xpower?

    Started by rz56, 4th April 2008 03:39
    • Replies: 2
    • Views: 692
    4th April 2008, 04:21 Go to last post
  14. Closed: Pin mapping with an IP in XPS

    Started by Rob B, 4th April 2008 01:39
    • Replies: 0
    • Views: 768
    4th April 2008, 01:39 Go to last post
  15. Closed: can anybody help to write vhdl code

    Started by ztanish, 20th March 2008 04:48
    • Replies: 2
    • Views: 1,090
    3rd April 2008, 15:45 Go to last post
  16. Closed: Xilinx synthesis & CLOCK signals

    Started by Mirzaaur, 2nd April 2008 13:24
    • Replies: 2
    • Views: 1,014
    3rd April 2008, 10:48 Go to last post
  17. Closed: AES Code in VERILOG -- URGENT

    Started by iti_malik, 1st April 2008 18:55
    • Replies: 1
    • Views: 4,554
    3rd April 2008, 10:09 Go to last post
  18. Closed: Warning : :PhysDesignRules:372 - Gated clock.? what is it?

    Started by xtcx, 29th March 2008 11:43
    • Replies: 5
    • Views: 14,582
    3rd April 2008, 10:03 Go to last post
  19. Closed: requency range of SPARTAN 3E XC3S500E

    Started by neefa, 3rd April 2008 05:12
    • Replies: 2
    • Views: 1,062
    3rd April 2008, 09:51 Go to last post
  20. Closed: How to insert library function to find sum.....

    Started by Sreya39, 3rd April 2008 07:17
    • Replies: 1
    • Views: 776
    3rd April 2008, 07:58 Go to last post
  21. Closed: VGA Horizontal counter, Behavioral VHDL code

    Started by BlackOps, 3rd March 2008 09:33
    • Replies: 11
    • Views: 8,715
    2nd April 2008, 21:55 Go to last post
  22. Closed: order of the FIR filter - design code in HDL

    Started by reninroy, 1st April 2008 08:38
    • Replies: 2
    • Views: 1,360
    2nd April 2008, 20:57 Go to last post
  23. Closed: Writing to DDR RAM on Virtex II Pro Board on PLB Bus

    Started by adamba, 31st March 2008 04:21
    • Replies: 2
    • Views: 2,252
    2nd April 2008, 20:40 Go to last post
  24. Closed: any one want programming for lattice cpld isp 1016

    Started by muruganshanjai, 2nd April 2008 17:09
    • Replies: 0
    • Views: 1,535
    2nd April 2008, 17:09 Go to last post
  25. Closed: Moving message display on lcd using vhdl

    Started by dzongo, 28th March 2008 14:49
    • Replies: 2
    • Views: 2,747
    2nd April 2008, 12:14 Go to last post
  26. Closed: How to read\write data using asynchronous clk?

    Started by xtcx, 25th March 2008 05:37
    • Replies: 9
    • Views: 1,892
    2nd April 2008, 12:00 Go to last post
  27. Closed: verilog code to find mean of 20 numbers

    Started by Sreya39, 27th March 2008 06:34
    • Replies: 14
    • Views: 3,922
    2nd April 2008, 11:17 Go to last post
  28. Closed: [REQ] - experience with FPGA with built in SerDes

    Started by kobik, 12th March 2003 17:34
    • Replies: 9
    • Views: 2,117
    2nd April 2008, 09:14 Go to last post
  29. Closed: What are the methods for SSB?

    Started by nktu, 1st March 2008 10:40
    • Replies: 3
    • Views: 911
    2nd April 2008, 07:29 Go to last post
  30. Closed: web_sever problem,thanks

    Started by 8a112, 1st April 2008 05:57
    • Replies: 1
    • Views: 1,058
    2nd April 2008, 05:00 Go to last post