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Threads 15001 to 15030 of 21684

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Binary to 7-segment with Decoder

    Started by afouladi86, 9th March 2008 21:16
    • Replies: 2
    • Views: 2,365
    11th March 2008, 07:48 Go to last post
  2. Closed: Regarding Spartan3A DSP Replacement

    Started by madu2023, 10th March 2008 08:20
    • Replies: 1
    • Views: 673
    11th March 2008, 07:43 Go to last post
  3. Closed: Regarding Spartan3A DSP Replacement

    Started by madu2023, 10th March 2008 09:01
    • Replies: 1
    • Views: 736
    11th March 2008, 07:42 Go to last post
  4. Closed: Comparison of booth, wallace and their combination

    Started by samiksha, 11th March 2008 06:58
    • Replies: 0
    • Views: 1,018
    11th March 2008, 06:58 Go to last post
  5. Closed: How to see the fractional part of division simulation

    Started by sameem_shabbir, 11th March 2008 04:57
    • Replies: 2
    • Views: 958
    11th March 2008, 06:28 Go to last post
  6. Closed: FPGA KIT design hlp ?

    Started by manish12, 10th March 2008 15:54
    • Replies: 3
    • Views: 770
    10th March 2008, 21:34 Go to last post
  7. Closed: DLP Design FPGA - anny experienced user?

    Started by nsakan, 10th March 2008 21:21
    • Replies: 0
    • Views: 741
    10th March 2008, 21:21 Go to last post
  8. Closed: DCM parameters [Virtex2 pro]

    Started by BlackOps, 10th March 2008 12:33
    • Replies: 3
    • Views: 969
    10th March 2008, 20:46 Go to last post
  9. Closed: Reading .exe file in testbench

    Started by sagar_saga01, 10th March 2008 19:07
    • Replies: 1
    • Views: 1,000
    10th March 2008, 19:59 Go to last post
  10. Closed: NLMS algorithm for echo cancellation in Verilog/VHDL

    Started by mahdi.ebrahimzadeh, 10th March 2008 14:37
    • Replies: 0
    • Views: 1,611
    10th March 2008, 14:37 Go to last post
  11. Closed: How to solve this FF/Latch trimming warning (XST 1895)?

    Started by mindstream, 10th March 2008 09:22
    • Replies: 2
    • Views: 1,920
    10th March 2008, 14:31 Go to last post
  12. Closed: Regarding Spartan3A DSP Replacement

    Started by madu2023, 10th March 2008 09:10
    • Replies: 1
    • Views: 855
    10th March 2008, 14:24 Go to last post
  13. Closed: How to fix multi source errors in Verilog code?

    Started by andrew257, 9th March 2008 21:02
    • Replies: 1
    • Views: 979
    9th March 2008, 21:30 Go to last post
  14. Closed: Introductory document about STA

    Started by verilog.course, 9th March 2008 21:28
    • Replies: 0
    • Views: 567
    9th March 2008, 21:28 Go to last post
  15. Closed: Looking for modbus VHDL code

    Started by manish12, 9th March 2008 18:34
    • Replies: 0
    • Views: 1,243
    9th March 2008, 18:34 Go to last post
  16. Closed: Quartus TRAINING : ALTERA

    Started by priyankguddu, 9th March 2008 13:39
    • Replies: 0
    • Views: 1,219
    9th March 2008, 13:39 Go to last post
  17. Closed: regarding the ethernet when i configured through FPGA

    Started by rajsrikanth, 8th March 2008 10:28
    • Replies: 3
    • Views: 869
    9th March 2008, 13:09 Go to last post
    • Replies: 1
    • Views: 1,708
    9th March 2008, 13:06 Go to last post
  18. Closed: Help me out with a VHDL code issue

    Started by mrdotcom1, 3rd March 2008 06:31
    • Replies: 5
    • Views: 997
    8th March 2008, 21:24 Go to last post
  19. Closed: Can I increase the size of RAM, as I need some BRAM?

    Started by sameem_shabbir, 6th March 2008 20:12
    • Replies: 5
    • Views: 947
    8th March 2008, 21:18 Go to last post
  20. Closed: How to read data from Virtex 2P board to PC ?

    Started by pd, 5th March 2008 23:05
    • Replies: 3
    • Views: 1,121
    7th March 2008, 22:41 Go to last post
  21. Closed: Help regarding Level shifter IC

    Started by sita, 27th January 2008 16:19
    • Replies: 2
    • Views: 1,251
    7th March 2008, 22:38 Go to last post
  22. Closed: Does anyone still do design in (Xilinx)ABEL or (Altera) AHDL

    Started by modelsim62c, 13th April 2007 03:26
    • Replies: 2
    • Views: 1,633
    7th March 2008, 20:12 Go to last post
  23. Closed: partial reconfiguration on Spartan 3

    Started by samcheetah, 21st February 2008 13:17
    • Replies: 1
    • Views: 1,208
    7th March 2008, 15:51 Go to last post
  24. Closed: Looking for VHDL code for adder

    Started by sumant.thapliyal, 15th August 2007 14:13
    • Replies: 7
    • Views: 37,702
    7th March 2008, 15:39 Go to last post
  25. Closed: Where to start learning FPGA ?

    Started by hamed_sotoudi, 22nd October 2007 14:03
    • Replies: 18
    • Views: 3,747
    7th March 2008, 14:40 Go to last post
  26. Closed: What is the effect of fan-in in acircuit?

    Started by sachinmaheshwari, 29th February 2008 11:52
    • Replies: 4
    • Views: 888
    7th March 2008, 14:01 Go to last post
    • Replies: 5
    • Views: 971
    7th March 2008, 14:01 Go to last post
  27. Closed: parallel to serial converter

    Started by neefa, 7th March 2008 10:22
    • Replies: 6
    • Views: 1,255
    7th March 2008, 13:59 Go to last post
  28. Closed: Image Conversion To Hex Format

    Started by sameem_shabbir, 29th February 2008 04:59
    • Replies: 3
    • Views: 1,236
    7th March 2008, 12:42 Go to last post