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Threads 15001 to 15030 of 21779

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: How to download image on to the fpga

    Started by grky1602, 25th March 2008 22:11
    • Replies: 2
    • Views: 852
    deepu_s_s
    27th March 2008, 12:08 Go to last post

  2. Closed: interfacing two blocks where both transfer data in posedge

    Started by dilan2005, 21st March 2008 08:26
    • Replies: 3
    • Views: 799
    jossion
    27th March 2008, 11:47 Go to last post

  3. Closed: Is generate function syntheisizable or not in VHDL?

    Started by reninroy, 18th March 2008 08:50
    • Replies: 3
    • Views: 802
    kvingle
    27th March 2008, 09:15 Go to last post

  4. Closed: fpga design --------help

    Started by hamran, 9th March 2008 17:13
    • Replies: 3
    • Views: 850
    ylscqu
    27th March 2008, 04:37 Go to last post

  5. Closed: Xilinx Virtex-5 16bit/125M PCIE PIPE Gen1 wrapper

    Started by openwindows, 27th March 2008 02:45
    • Replies: 0
    • Views: 823
    openwindows
    27th March 2008, 02:45 Go to last post

  6. Closed: why more clock skew when use DCM rather than no DCM?

    Started by gauz, 25th March 2008 15:50
    • Replies: 2
    • Views: 1,259
    gauz
    26th March 2008, 15:12 Go to last post

  7. Closed: need help with interface LCD to FPGA board

    Started by t5bz9, 25th March 2008 19:54
    • Replies: 3
    • Views: 1,235
    shakeelsultan
    26th March 2008, 14:04 Go to last post

  8. Closed: How to pass the values in Verilog during run time?

    Started by balan, 26th March 2008 10:07
    • Replies: 2
    • Views: 837
    balan
    26th March 2008, 13:56 Go to last post

  9. Closed: input data to fpga....

    Started by bcdeepak, 17th March 2008 13:08
    • Replies: 6
    • Views: 1,137
    muralicrl
    26th March 2008, 10:07 Go to last post

  10. Closed: Regarding dualport RAM

    Started by kavitha_bonthu, 15th March 2008 15:02
    • Replies: 6
    • Views: 977
    muralicrl
    26th March 2008, 09:47 Go to last post

  11. Closed: How does FPGA implement the function?

    Started by sandeep_sggs, 15th March 2008 05:09
    • Replies: 2
    • Views: 792
    muralicrl
    26th March 2008, 07:20 Go to last post

  12. Closed: how to convert .sue files to .sdb format (tspice)

    Started by sripriyagn, 25th March 2008 13:32
    • Replies: 0
    • Views: 795
    sripriyagn
    25th March 2008, 13:32 Go to last post

  13. Closed: What is meant by optimal scheduling vector and projection vector in systolic array?

    Started by simu, 25th March 2008 13:03
    • Replies: 0
    • Views: 799
    simu
    25th March 2008, 13:03 Go to last post

  14. Closed: Help me declare and initialize an array

    Started by anandanips, 19th March 2008 06:36
    • Replies: 4
    • Views: 1,347
    cherjier
    25th March 2008, 04:52 Go to last post

  15. Closed: CAD for VLSI Simulation Thermal

    Started by omar-malek, 25th March 2008 02:10
    • Replies: 0
    • Views: 660
    omar-malek
    25th March 2008, 02:10 Go to last post

  16. Closed: Xilinx MIG2.0 DDR2 memory controller

    Started by adamsogood, 7th March 2008 04:20
    • Replies: 5
    • Views: 2,782
    adamsogood
    24th March 2008, 19:00 Go to last post

  17. Closed: Info about router design using BDDs

    Started by anandanips, 24th March 2008 09:46
    • Replies: 0
    • Views: 572
    anandanips
    24th March 2008, 09:46 Go to last post

  18. Closed: xilinx (xst) simulator

    Started by anandanips, 24th March 2008 09:39
    • Replies: 0
    • Views: 986
    anandanips
    24th March 2008, 09:39 Go to last post

  19. Closed: parallel FFT in VHDL. help me

    Started by francescoabb, 13th February 2008 16:34
    • Replies: 3
    • Views: 1,766
    saint202
    23rd March 2008, 18:52 Go to last post

  20. Closed: XC5202 and ISE howto?

    Started by nsakan, 23rd March 2008 11:19
    • Replies: 0
    • Views: 499
    nsakan
    23rd March 2008, 11:19 Go to last post

  21. Closed: Question about fanout in Altera Stratix II

    Started by jzhangsun, 22nd March 2008 16:22
    • Replies: 1
    • Views: 941
    FvM
    22nd March 2008, 16:31 Go to last post

  22. Closed: FFT core with magnitude data only?

    Started by Rob B, 19th March 2008 22:01
    • Replies: 5
    • Views: 2,270
    Rob B
    22nd March 2008, 14:37 Go to last post

  23. Closed: How to display the image from the reflected signal of RADAR?

    Started by honnaraj.t, 11th March 2008 09:55
    • Replies: 3
    • Views: 889
    sameem_shabbir
    22nd March 2008, 10:56 Go to last post

  24. Closed: Can I use Chipscope with ISE webpack 9.1?

    Started by rsrinivas, 5th February 2007 09:33
    • Replies: 6
    • Views: 1,733
    mrdotcom1
    22nd March 2008, 10:20 Go to last post

  25. Closed: VHDL Loop error: Process Statement must contain only one Wait Statement

    Started by syyang85, 21st March 2008 13:56
    • Replies: 3
    • Views: 4,193
    FvM
    21st March 2008, 19:26 Go to last post

  26. Closed: How to design a modbus protocol using vhdl?

    Started by manish12, 20th March 2008 14:40
    • Replies: 3
    • Views: 5,262
    benradu
    21st March 2008, 14:48 Go to last post

  27. Closed: Help me do IRIG-B time code generator and decoder

    Started by shivakumay.gy, 21st March 2008 11:45
    • Replies: 0
    • Views: 1,284
    shivakumay.gy
    21st March 2008, 11:45 Go to last post

  28. Closed: Problem with model sim

    Started by deepu_s_s, 18th March 2008 07:17
    • Replies: 7
    • Views: 1,447
    echo47
    20th March 2008, 22:17 Go to last post

  29. [SOLVED] CPLD clock source question

    Started by LaszloF, 30th January 2008 10:08
    • Replies: 8
    • Views: 4,029
    carbon9
    20th March 2008, 19:33 Go to last post

  30. Closed: How to check file existence in Verilog

    Started by vijay82, 20th March 2008 16:44
    • Replies: 1
    • Views: 7,289
    banjo
    20th March 2008, 19:00 Go to last post
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