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Threads 15001 to 15030 of 22100

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: help in system generator

    Started by ck_nandy, 21st May 2008 12:06
    • Replies: 3
    • Views: 888
    26th May 2008, 20:00 Go to last post
  2. Closed: VERILOG CODE FOR BCD TO DECODER????

    Started by dogarsahab, 26th May 2008 14:45
    • Replies: 1
    • Views: 9,262
    26th May 2008, 16:00 Go to last post
  3. Closed: Modelsim Limited Visibility Region

    Started by akrout.achraf, 26th May 2008 13:11
    • Replies: 0
    • Views: 2,285
    26th May 2008, 13:11 Go to last post
  4. Closed: Altera / Xlinx FPGA Beginer

    Started by boseji, 24th May 2008 05:22
    • Replies: 5
    • Views: 1,514
    26th May 2008, 07:18 Go to last post
  5. Closed: can we assign variables in gen? (specman doubt)

    Started by vinod_g, 25th January 2008 10:45
    • Replies: 1
    • Views: 995
    26th May 2008, 04:54 Go to last post
  6. Closed: Generate Ethernet frame

    Started by Thoma HAUC, 25th May 2008 19:31
    • Replies: 0
    • Views: 1,026
    25th May 2008, 19:31 Go to last post
  7. Closed: VHDL code for quadrature NCO

    Started by missbirdie, 21st May 2008 19:46
    • Replies: 9
    • Views: 4,145
    25th May 2008, 18:12 Go to last post
  8. Closed: Verilog ebooks about progamming, desing and testbench

    Started by Tom2, 22nd May 2008 14:23
    • Replies: 1
    • Views: 911
    25th May 2008, 04:13 Go to last post
  9. Closed: Problem Using Dsp tools software(Acel dsp)

    Started by BAT_MAN, 24th May 2008 17:19
    • Replies: 0
    • Views: 726
    24th May 2008, 17:19 Go to last post
  10. Closed: Problem in device list of ISE 10.1

    Started by Mehdi1357, 24th May 2008 11:37
    • Replies: 1
    • Views: 1,854
    24th May 2008, 14:13 Go to last post
  11. Closed: what is the benefit of unsynthesizable code?

    Started by moh_monem43, 19th May 2008 15:25
    • Replies: 3
    • Views: 909
    24th May 2008, 11:22 Go to last post
  12. Closed: Replication operator symbol - in VHDL language

    Started by vnandanece, 24th May 2008 10:33
    • Replies: 1
    • Views: 4,393
    24th May 2008, 11:03 Go to last post
  13. Closed: implementation pipeline cpu with verilog

    Started by bidgol, 21st May 2008 18:22
    • Replies: 3
    • Views: 7,035
    24th May 2008, 10:35 Go to last post
  14. Closed: A very small CPU, 40 point donation

    Started by Sadegh.j, 21st May 2008 04:41
    • Replies: 5
    • Views: 1,122
    24th May 2008, 07:57 Go to last post
  15. Closed: MISER / TURBO Bit - CUPL FUSE statement

    Started by Pedros, 23rd May 2008 16:14
    • Replies: 0
    • Views: 840
    23rd May 2008, 16:14 Go to last post
  16. Closed: NEXYS2 Spartan 3E LED issue.

    Started by Rob B, 5th March 2008 21:10
    • Replies: 13
    • Views: 6,980
    23rd May 2008, 15:15 Go to last post
  17. Closed: webcam interfacing on fpga

    Started by thelectronics, 23rd May 2008 10:26
    • Replies: 0
    • Views: 1,162
    23rd May 2008, 10:26 Go to last post
  18. Closed: anyone can help m in edk

    Started by ck_nandy, 28th April 2008 10:28
    • Replies: 3
    • Views: 1,098
    23rd May 2008, 07:48 Go to last post
  19. Closed: How to design a simple VGA card?

    Started by n38, 19th May 2008 10:09
    • Replies: 1
    • Views: 1,056
    22nd May 2008, 16:48 Go to last post
  20. Closed: need a simple source code

    Started by farrokhiyan, 22nd May 2008 09:11
    • Replies: 1
    • Views: 1,064
    22nd May 2008, 16:27 Go to last post
  21. Closed: two clock frequency operation

    Started by rajsrikanth, 21st May 2008 12:52
    • Replies: 4
    • Views: 858
    22nd May 2008, 10:09 Go to last post
    • Replies: 1
    • Views: 2,083
    22nd May 2008, 08:07 Go to last post
  22. Closed: Help me plz......Veriolg code to find division.....

    Started by Sreya39, 22nd May 2008 08:03
    • Replies: 0
    • Views: 716
    22nd May 2008, 08:03 Go to last post
  23. Closed: HELP!!! Error message in Xilinx ISE 8.2i

    Started by childs, 21st May 2008 06:09
    • Replies: 2
    • Views: 1,191
    22nd May 2008, 05:27 Go to last post
  24. Closed: Manchester encoder /decoder

    Started by vintujose, 20th May 2008 16:28
    • Replies: 1
    • Views: 5,511
    21st May 2008, 13:20 Go to last post
  25. Closed: please help.....vhdl code for dsp processor

    Started by sara_123, 25th April 2008 08:02
    • Replies: 14
    • Views: 1,871
    21st May 2008, 11:40 Go to last post
  26. Closed: How to make an use a memory table in VHDL?

    Started by Oana, 6th May 2008 14:00
    • Replies: 4
    • Views: 1,251
    21st May 2008, 09:56 Go to last post
  27. Closed: division in verilog - ok in sumilation, error if synthesized

    Started by nidahas, 21st May 2008 06:22
    • Replies: 3
    • Views: 2,045
    21st May 2008, 09:24 Go to last post
  28. Closed: Please clear my doubts

    Started by deepu_s_s, 19th May 2008 18:35
    • Replies: 7
    • Views: 1,116
    21st May 2008, 04:28 Go to last post
  29. Closed: Implemenration of RAMDAC in FPGA

    Started by rahul99_spil, 20th May 2008 14:39
    • Replies: 2
    • Views: 1,085
    20th May 2008, 14:51 Go to last post