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Threads 15001 to 15030 of 22012

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Problem with system generator

    Started by deepu_s_s, 26th April 2008 12:16
    • Replies: 5
    • Views: 1,650
    5th May 2008, 08:27 Go to last post
  2. Closed: Urgent help required .... Regarding lpm_divide

    Started by sharada.144, 5th May 2008 05:52
    • Replies: 0
    • Views: 1,396
    5th May 2008, 05:52 Go to last post
  3. Closed: LIFO in qu(at)rtus, how to simulate

    Started by e_ali_e, 5th May 2008 05:25
    • Replies: 0
    • Views: 858
    5th May 2008, 05:25 Go to last post
  4. Closed: Floating Point FFT CORE ???

    Started by reza_10, 16th April 2008 21:11
    • Replies: 2
    • Views: 1,056
    4th May 2008, 15:42 Go to last post
  5. Closed: advice and help needed..

    Started by asoom, 3rd May 2008 09:52
    • Replies: 3
    • Views: 808
    4th May 2008, 15:11 Go to last post
  6. Closed: How to replace 74ACT8990 for Verilog source code

    Started by huxiaoping, 4th May 2008 08:57
    • Replies: 0
    • Views: 701
    4th May 2008, 08:57 Go to last post
  7. Closed: How to reuse component (multiplier) for calculation?

    Started by triump.ar, 1st May 2008 18:48
    • Replies: 1
    • Views: 799
    4th May 2008, 01:19 Go to last post
  8. Closed: Problem with using Lattice gal22v10 program

    Started by Fedail, 3rd May 2008 13:21
    • Replies: 0
    • Views: 886
    3rd May 2008, 13:21 Go to last post
    • Replies: 3
    • Views: 1,360
    3rd May 2008, 12:08 Go to last post
  9. Closed: initialize jtag chain error.

    Started by ilikebbs, 30th April 2008 10:03
    • Replies: 2
    • Views: 1,316
    3rd May 2008, 09:42 Go to last post
    • Replies: 0
    • Views: 547
    2nd May 2008, 15:30 Go to last post
  10. Closed: Need info about Zefant LC3E-100 board

    Started by dilan2005, 2nd May 2008 13:36
    • Replies: 0
    • Views: 1,080
    2nd May 2008, 13:36 Go to last post
  11. Closed: Please help me about a problem with LPM library in Quartus!

    Started by lts85, 2nd May 2008 05:52
    • Replies: 2
    • Views: 1,171
    2nd May 2008, 08:21 Go to last post
  12. Closed: How to use $rand() in Verilog ?

    Started by deepu_s_s, 2nd May 2008 05:02
    • Replies: 1
    • Views: 4,448
    2nd May 2008, 07:27 Go to last post
  13. Closed: reg - project details.....

    Started by money_kandan2004, 2nd May 2008 06:35
    • Replies: 0
    • Views: 592
    2nd May 2008, 06:35 Go to last post
  14. Closed: New Kind of Problem with Model Sim

    Started by deepu_s_s, 1st May 2008 04:15
    • Replies: 2
    • Views: 8,754
    2nd May 2008, 05:12 Go to last post
  15. Closed: FPGA DESIGN OF ELECTRONIC VOTING SYSTEM

    Started by smqasim, 27th April 2008 13:59
    • Replies: 8
    • Views: 1,974
    1st May 2008, 19:59 Go to last post
  16. Closed: Two's complement using minimum hardware

    Started by lordsathish, 29th April 2008 06:44
    • Replies: 5
    • Views: 4,491
    30th April 2008, 12:42 Go to last post
  17. Closed: `timescale usage in Verilog?

    Started by want2LearnVlsi, 28th April 2008 11:38
    • Replies: 3
    • Views: 22,772
    30th April 2008, 12:24 Go to last post
  18. Closed: Verilog bus help required

    Started by davidgrm, 29th April 2008 22:08
    • Replies: 1
    • Views: 867
    30th April 2008, 11:58 Go to last post
  19. Closed: rom/ram implementation ..

    Started by prashant_sharma, 29th April 2008 21:35
    • Replies: 1
    • Views: 1,101
    30th April 2008, 11:32 Go to last post
  20. Closed: bus counter in digital electronics

    Started by vijayganesh, 29th April 2008 06:49
    • Replies: 2
    • Views: 970
    30th April 2008, 10:51 Go to last post
  21. Closed: Help me with the code_ parallel to serial converter...

    Started by sharada.144, 30th April 2008 06:01
    • Replies: 2
    • Views: 1,023
    30th April 2008, 08:47 Go to last post
  22. Closed: How to distinguish between two different SLAVE devices?

    Started by xie.qiang, 30th April 2008 01:12
    • Replies: 1
    • Views: 776
    30th April 2008, 07:02 Go to last post
  23. Closed: CoolRunner core voltage when output shorted to ground

    Started by kender, 30th April 2008 02:53
    • Replies: 0
    • Views: 628
    30th April 2008, 02:53 Go to last post
  24. Closed: UDP packet losses after adding modules to the system

    Started by dilan2005, 29th April 2008 20:38
    • Replies: 0
    • Views: 1,073
    29th April 2008, 20:38 Go to last post
  25. Closed: Help needed.. parallel to serial converter in VHDL

    Started by sharada.144, 29th April 2008 09:15
    • Replies: 3
    • Views: 3,069
    29th April 2008, 14:54 Go to last post
  26. Closed: Help me make a counter with 2 inputs

    Started by shadeslayer, 23rd April 2008 19:24
    • Replies: 5
    • Views: 943
    29th April 2008, 12:08 Go to last post
  27. Closed: Accessing SRAM or SDRAM in Altera DE 1 Board

    Started by cbtarunjai87, 25th April 2008 14:54
    • Replies: 5
    • Views: 5,615
    29th April 2008, 10:47 Go to last post
  28. Closed: "non-standard utilization" of APEX NIOS 2 board

    Started by childs, 29th April 2008 02:52
    • Replies: 1
    • Views: 895
    29th April 2008, 06:47 Go to last post