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Threads 15001 to 15030 of 22001

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Need info about Zefant LC3E-100 board

    Started by dilan2005, 2nd May 2008 13:36
    • Replies: 0
    • Views: 1,077
    2nd May 2008, 13:36 Go to last post
  2. Closed: Please help me about a problem with LPM library in Quartus!

    Started by lts85, 2nd May 2008 05:52
    • Replies: 2
    • Views: 1,170
    2nd May 2008, 08:21 Go to last post
  3. Closed: How to use $rand() in Verilog ?

    Started by deepu_s_s, 2nd May 2008 05:02
    • Replies: 1
    • Views: 4,444
    2nd May 2008, 07:27 Go to last post
  4. Closed: reg - project details.....

    Started by money_kandan2004, 2nd May 2008 06:35
    • Replies: 0
    • Views: 591
    2nd May 2008, 06:35 Go to last post
  5. Closed: New Kind of Problem with Model Sim

    Started by deepu_s_s, 1st May 2008 04:15
    • Replies: 2
    • Views: 8,736
    2nd May 2008, 05:12 Go to last post
  6. Closed: FPGA DESIGN OF ELECTRONIC VOTING SYSTEM

    Started by smqasim, 27th April 2008 13:59
    • Replies: 8
    • Views: 1,970
    1st May 2008, 19:59 Go to last post
  7. Closed: Two's complement using minimum hardware

    Started by lordsathish, 29th April 2008 06:44
    • Replies: 5
    • Views: 4,472
    30th April 2008, 12:42 Go to last post
  8. Closed: `timescale usage in Verilog?

    Started by want2LearnVlsi, 28th April 2008 11:38
    • Replies: 3
    • Views: 22,696
    30th April 2008, 12:24 Go to last post
  9. Closed: Verilog bus help required

    Started by davidgrm, 29th April 2008 22:08
    • Replies: 1
    • Views: 865
    30th April 2008, 11:58 Go to last post
  10. Closed: rom/ram implementation ..

    Started by prashant_sharma, 29th April 2008 21:35
    • Replies: 1
    • Views: 1,099
    30th April 2008, 11:32 Go to last post
  11. Closed: bus counter in digital electronics

    Started by vijayganesh, 29th April 2008 06:49
    • Replies: 2
    • Views: 970
    30th April 2008, 10:51 Go to last post
  12. Closed: Help me with the code_ parallel to serial converter...

    Started by sharada.144, 30th April 2008 06:01
    • Replies: 2
    • Views: 1,020
    30th April 2008, 08:47 Go to last post
  13. Closed: How to distinguish between two different SLAVE devices?

    Started by xie.qiang, 30th April 2008 01:12
    • Replies: 1
    • Views: 773
    30th April 2008, 07:02 Go to last post
  14. Closed: CoolRunner core voltage when output shorted to ground

    Started by kender, 30th April 2008 02:53
    • Replies: 0
    • Views: 624
    30th April 2008, 02:53 Go to last post
  15. Closed: UDP packet losses after adding modules to the system

    Started by dilan2005, 29th April 2008 20:38
    • Replies: 0
    • Views: 1,070
    29th April 2008, 20:38 Go to last post
  16. Closed: Help needed.. parallel to serial converter in VHDL

    Started by sharada.144, 29th April 2008 09:15
    • Replies: 3
    • Views: 3,060
    29th April 2008, 14:54 Go to last post
  17. Closed: Help me make a counter with 2 inputs

    Started by shadeslayer, 23rd April 2008 19:24
    • Replies: 5
    • Views: 933
    29th April 2008, 12:08 Go to last post
  18. Closed: Accessing SRAM or SDRAM in Altera DE 1 Board

    Started by cbtarunjai87, 25th April 2008 14:54
    • Replies: 5
    • Views: 5,609
    29th April 2008, 10:47 Go to last post
  19. Closed: "non-standard utilization" of APEX NIOS 2 board

    Started by childs, 29th April 2008 02:52
    • Replies: 1
    • Views: 893
    29th April 2008, 06:47 Go to last post
  20. Closed: Modelsim error - assuming recursive instantiation

    Started by kalyansrinivas, 29th April 2008 05:22
    • Replies: 0
    • Views: 1,945
    29th April 2008, 05:22 Go to last post
  21. Closed: insufficient LE units

    Started by childs, 28th April 2008 05:08
    • Replies: 3
    • Views: 709
    29th April 2008, 02:55 Go to last post
  22. Closed: Video Processing in Verilog

    Started by DrooPyKoRn, 29th April 2008 00:26
    • Replies: 0
    • Views: 845
    29th April 2008, 00:26 Go to last post
  23. Closed: Need VHDL code for FSK demodulator

    Started by hamed_sotoudi, 28th April 2008 14:33
    • Replies: 1
    • Views: 2,846
    28th April 2008, 21:54 Go to last post
  24. Closed: VHDL code for RAM MT48LC16M4A2

    Started by hamed_sotoudi, 28th April 2008 14:31
    • Replies: 0
    • Views: 1,127
    28th April 2008, 14:31 Go to last post
  25. Closed: System generator applications

    Started by arunkumar_sek, 28th April 2008 10:33
    • Replies: 2
    • Views: 905
    28th April 2008, 12:20 Go to last post
  26. Closed: Project titles in SPARTAN 3E FPGA

    Started by arunkumar_sek, 28th April 2008 10:29
    • Replies: 0
    • Views: 758
    28th April 2008, 10:29 Go to last post
  27. Closed: How to plot the contains of RAM on VGA screen?

    Started by nimarc, 26th April 2008 14:37
    • Replies: 2
    • Views: 2,271
    27th April 2008, 17:12 Go to last post
  28. Closed: Parellel ro serial converter

    Started by sagar_saga01, 27th April 2008 14:12
    • Replies: 1
    • Views: 811
    27th April 2008, 14:42 Go to last post
  29. Closed: low power FPGA based DSP modules

    Started by rz56, 27th April 2008 07:18
    • Replies: 0
    • Views: 785
    27th April 2008, 07:18 Go to last post
  30. Closed: VHDL Code for Linear Feedback Shift Resistor(LFSR)

    Started by Sultan1551, 26th April 2008 17:42
    • Replies: 1
    • Views: 6,910
    26th April 2008, 20:44 Go to last post