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Threads 15001 to 15030 of 21881

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Why we use high resolution accumulator in Xilinx DDS (NCO)?

    Started by alzomor, 10th April 2008 09:14
    • Replies: 3
    • Views: 2,039
    10th April 2008, 10:57 Go to last post
  2. Closed: Base System Builder example fails

    Started by BlackOps, 23rd March 2008 15:44
    • Replies: 9
    • Views: 1,878
    10th April 2008, 09:37 Go to last post
  3. Closed: DDR SDRAM controller operation and Virtex2 Pro

    Started by BlackOps, 9th April 2008 18:33
    • Replies: 2
    • Views: 2,876
    10th April 2008, 07:14 Go to last post
  4. Closed: multiple clock divider

    Started by triump.ar, 9th April 2008 16:58
    • Replies: 5
    • Views: 1,817
    10th April 2008, 05:20 Go to last post
  5. Closed: how to check delay in interrrupts?

    Started by samiksha, 8th April 2008 08:54
    • Replies: 3
    • Views: 740
    10th April 2008, 03:16 Go to last post
  6. Closed: What's wrong with my VHDL code

    Started by deepu_s_s, 8th April 2008 21:17
    • Replies: 4
    • Views: 4,929
    9th April 2008, 18:03 Go to last post
  7. Closed: Problem in Instruction Execution!!!

    Started by shakeelsultan, 9th April 2008 14:08
    • Replies: 1
    • Views: 583
    9th April 2008, 15:02 Go to last post
  8. Closed: Looking for ieee1149 specifications

    Started by cooljack, 9th April 2008 10:54
    • Replies: 0
    • Views: 682
    9th April 2008, 10:54 Go to last post
  9. Closed: Timing constraint violations when crossing clock domains?

    Started by davr, 8th April 2008 22:15
    • Replies: 3
    • Views: 1,588
    9th April 2008, 09:49 Go to last post
  10. Closed: Help in choosing FPGA board

    Started by deepu_s_s, 2nd April 2008 04:25
    • Replies: 5
    • Views: 899
    9th April 2008, 03:48 Go to last post
  11. Closed: CLOCK MULTIPLIER AND DIVIDER

    Started by suru, 28th March 2008 11:52
    • Replies: 10
    • Views: 6,080
    9th April 2008, 01:09 Go to last post
  12. Closed: Help me with NDT basic project using FPGA

    Started by shadeslayer, 21st March 2008 06:40
    • Replies: 7
    • Views: 1,017
    9th April 2008, 01:06 Go to last post
  13. Closed: How to measure throughput of a circuit?

    Started by sagar_saga01, 7th April 2008 06:17
    • Replies: 1
    • Views: 586
    9th April 2008, 01:00 Go to last post
  14. Closed: Looking for a opensource USB HID core

    Started by mobile-it, 10th February 2008 12:20
    • Replies: 3
    • Views: 2,112
    8th April 2008, 20:05 Go to last post
  15. Closed: New problems with EDK 9.1

    Started by BlackOps, 8th April 2008 19:04
    • Replies: 0
    • Views: 987
    8th April 2008, 19:04 Go to last post
    • Replies: 2
    • Views: 1,483
    8th April 2008, 17:54 Go to last post
  16. Closed: increasing speed in fpga and vhdl

    Started by m_pourfathi, 6th April 2008 07:35
    • Replies: 4
    • Views: 1,246
    8th April 2008, 12:34 Go to last post
  17. Closed: help to create picture on memory and display on vga monitor

    Started by honnaraj.t, 4th April 2008 05:39
    • Replies: 5
    • Views: 1,617
    8th April 2008, 12:26 Go to last post
  18. Closed: VGA controller and FMS3818 video chip

    Started by BlackOps, 12th March 2008 15:22
    • Replies: 4
    • Views: 5,134
    8th April 2008, 12:08 Go to last post
  19. Closed: How I can read/write to the following blockram RAM model ?

    Started by RRRED, 5th April 2008 22:52
    • Replies: 3
    • Views: 1,231
    8th April 2008, 11:22 Go to last post
  20. Closed: Device architecture selection in ISE 9.1 and EDK 9.1

    Started by BlackOps, 7th April 2008 18:19
    • Replies: 2
    • Views: 667
    8th April 2008, 10:06 Go to last post
  21. Closed: Help me convert VHDL code to Verilog

    Started by mondobongo, 7th April 2008 09:47
    • Replies: 3
    • Views: 1,099
    8th April 2008, 09:08 Go to last post
  22. Closed: Phase modulation of sine waveform in VHDL

    Started by rjai_pradha, 8th April 2008 08:26
    • Replies: 0
    • Views: 1,606
    8th April 2008, 08:26 Go to last post
  23. Closed: specify integer range and cycle through it

    Started by drifterz, 7th April 2008 15:21
    • Replies: 3
    • Views: 707
    8th April 2008, 08:14 Go to last post
  24. Closed: Problem with VHDL code to show symbol on LCD (Spartan 3E)

    Started by Alex_lynatik_, 3rd April 2008 22:48
    • Replies: 3
    • Views: 4,172
    8th April 2008, 06:22 Go to last post
  25. Closed: 1Hz clock source for CPLD

    Started by cosmicboy, 6th April 2008 02:56
    • Replies: 14
    • Views: 7,827
    8th April 2008, 03:57 Go to last post
  26. Closed: Xilinx Modelsim post-simulation error

    Started by xie.qiang, 7th April 2008 11:48
    • Replies: 1
    • Views: 1,048
    8th April 2008, 00:56 Go to last post
  27. Closed: ISE Resource Optimization

    Started by fahadislam2006, 3rd April 2008 19:26
    • Replies: 1
    • Views: 715
    7th April 2008, 21:24 Go to last post
  28. Closed: why use 120ohm resistor ld117 1.2v

    Started by dilan2005, 7th April 2008 16:20
    • Replies: 1
    • Views: 1,491
    7th April 2008, 18:59 Go to last post
  29. Closed: HI All help me please

    Started by venkatesankalidass, 5th April 2008 07:59
    • Replies: 1
    • Views: 724
    7th April 2008, 18:35 Go to last post