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Threads 91 to 120 of 22099

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Changing IP parameters in Vivado using HDL generics

    Started by shaiko, 13th December 2017 15:30
    • Replies: 13
    • Views: 1,041
    19th December 2017, 20:27 Go to last post
  2. help regarding fpga implemetation

    Started by kumar1988, 2nd September 2013 18:01
    • Replies: 16
    • Views: 1,254
    19th December 2017, 15:33 Go to last post
  3. Compile package into "ieee_proposed"

    Started by Hugo17, 19th December 2017 13:20
    • Replies: 1
    • Views: 373
    19th December 2017, 13:56 Go to last post
  4. Overcoming the 8:1 width conversion problem

    Started by shaiko, 17th December 2017 19:14
    • Replies: 5
    • Views: 618
    19th December 2017, 13:25 Go to last post
  5. Vivado HLS Experience

    Started by MarkPh, 1st December 2017 15:58
    • Replies: 6
    • Views: 1,280
    19th December 2017, 11:21 Go to last post
  6. AXI 4 Stream Data Width Converter

    Started by Vlad., 13th December 2017 08:22
    • Replies: 11
    • Views: 982
    18th December 2017, 14:49 Go to last post
    • Replies: 2
    • Views: 434
    18th December 2017, 04:39 Go to last post
  7. Scope of STA in FPGAs

    Started by hareesh007, 16th December 2017 13:26
    • Replies: 3
    • Views: 509
    18th December 2017, 03:49 Go to last post
    • Replies: 1
    • Views: 482
    18th December 2017, 02:40 Go to last post
  8. FPGA Based Car Game (Christmas Themed)

    Started by bwarlord01, 16th December 2017 15:26
    • Replies: 1
    • Views: 502
    16th December 2017, 19:46 Go to last post
  9. Vivado - math.real support

    Started by shaiko, 14th December 2017 12:37
    • Replies: 7
    • Views: 622
    15th December 2017, 13:12 Go to last post
  10. SSD performance gain

    Started by shaiko, 12th December 2017 17:27
    • Replies: 7
    • Views: 747
    14th December 2017, 09:45 Go to last post
  11. OpenCL GPU vs FPGA implementation

    Started by shaiko, 13th December 2017 01:23
    • Replies: 1
    • Views: 503
    13th December 2017, 16:35 Go to last post
  12. Generate desired random number in range in verilog

    Started by tayyab786, 27th November 2017 20:14
    2 Pages
    1 2
    • Replies: 20
    • Views: 2,582
    11th December 2017, 23:48 Go to last post
  13. FPGA USB Data software

    Started by expertengr, 9th December 2017 12:10
    • Replies: 5
    • Views: 778
    11th December 2017, 19:52 Go to last post
  14. [SOLVED] Round robin arbiter with ring counter.

    Started by ppko1233, 10th December 2017 14:26
    • Replies: 1
    • Views: 499
    11th December 2017, 16:48 Go to last post
  15. Improve UART resource usage

    Started by promach, 10th December 2017 12:41
    • Replies: 1
    • Views: 517
    11th December 2017, 02:09 Go to last post
  16. [SOLVED] logic : give value in which require decimal number represent

    Started by tayyab786, 10th December 2017 14:05
    • Replies: 5
    • Views: 590
    10th December 2017, 22:10 Go to last post
  17. Circuit protection with VHDL code

    Started by manush30, 6th December 2017 08:40
    • Replies: 9
    • Views: 895
    10th December 2017, 10:54 Go to last post
  18. ADS (advanced Design System) Xilinx FPGA model kit

    Started by Enrocinu, 10th December 2017 00:00
    • Replies: 0
    • Views: 546
    10th December 2017, 00:00 Go to last post
    • Replies: 2
    • Views: 473
    9th December 2017, 20:11 Go to last post
    • Replies: 4
    • Views: 911
    9th December 2017, 16:34 Go to last post
  19. choosing high speed data storage element

    Started by amin5659, 7th December 2017 16:42
    • Replies: 10
    • Views: 963
    9th December 2017, 10:39 Go to last post
  20. [SOLVED] How to load program to A54SX16A-PQG208M FPGA?

    Started by Mithun_K_Das, 5th December 2017 12:17
    • Replies: 13
    • Views: 1,369
    9th December 2017, 05:34 Go to last post
    • Replies: 4
    • Views: 561
    8th December 2017, 22:19 Go to last post
  21. How to run two module in series using verilog

    Started by kapaa, 7th December 2017 03:21
    • Replies: 6
    • Views: 725
    7th December 2017, 22:44 Go to last post
  22. FPGA-Based Christmas project

    Started by bwarlord01, 6th December 2017 19:29
    • Replies: 3
    • Views: 594
    7th December 2017, 02:46 Go to last post
  23. What is Most Economic FPGA?

    Started by Zerox100, 5th December 2017 16:04
    • Replies: 2
    • Views: 503
    6th December 2017, 12:59 Go to last post
    • Replies: 0
    • Views: 342
    6th December 2017, 12:18 Go to last post