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Threads 91 to 120 of 21959

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 4
    • Views: 483
    11th October 2017, 07:31 Go to last post
  1. Regarding connections in a CPLD schematic

    Started by garvind25, 10th October 2017 12:19
    • Replies: 6
    • Views: 465
    11th October 2017, 06:51 Go to last post
  2. Xilinx ISim - Post place and route simulation

    Started by NikosTS, 10th October 2017 16:08
    • Replies: 17
    • Views: 877
    11th October 2017, 00:32 Go to last post
    • Replies: 9
    • Views: 776
    10th October 2017, 16:32 Go to last post
  3. Trigger Signal in VHDL

    Started by nizdom, 9th October 2017 15:25
    • Replies: 6
    • Views: 433
    10th October 2017, 13:52 Go to last post
  4. dynamic array in verilog

    Started by tayyab786, 8th October 2017 09:16
    • Replies: 5
    • Views: 664
    10th October 2017, 12:32 Go to last post
  5. Help programming some Xilinx XC7236s

    Started by RobMUK, 9th October 2017 08:03
    • Replies: 2
    • Views: 400
    10th October 2017, 07:02 Go to last post
  6. Does Synopsys Certify support customer design boards?

    Started by lcf0451, 10th October 2017 03:21
    • Replies: 0
    • Views: 355
    10th October 2017, 03:21 Go to last post
  7. vhdl codes for adpll-plz help

    Started by manishpatkar, 8th October 2017 17:20
    • Replies: 3
    • Views: 496
    9th October 2017, 15:58 Go to last post
  8. Vhdl when else statement error

    Started by hareeshP, 9th October 2017 10:22
    • Replies: 4
    • Views: 315
    9th October 2017, 10:34 Go to last post
    • Replies: 0
    • Views: 339
    9th October 2017, 07:04 Go to last post
  9. Pipeline problem VHDL

    Started by nizdom, 6th October 2017 16:24
    • Replies: 7
    • Views: 662
    7th October 2017, 21:42 Go to last post
    • Replies: 2
    • Views: 466
    6th October 2017, 15:24 Go to last post
  10. [SOLVED] Altering some bits of a RAM location

    Started by rafimiet, 6th October 2017 06:53
    • Replies: 2
    • Views: 352
    6th October 2017, 08:10 Go to last post
  11. [SOLVED] clearing the contents of single port RAM

    Started by rafimiet, 4th October 2017 13:17
    • Replies: 13
    • Views: 656
    6th October 2017, 04:28 Go to last post
  12. [Synth 8-27] complex assignment not supported

    Started by rafimiet, 5th October 2017 10:41
    • Replies: 4
    • Views: 531
    6th October 2017, 04:23 Go to last post
    • Replies: 1
    • Views: 385
    4th October 2017, 14:05 Go to last post
  13. MAX II cpld volatile programming

    Started by hareeshP, 3rd October 2017 13:08
    • Replies: 4
    • Views: 509
    4th October 2017, 06:40 Go to last post
    • Replies: 2
    • Views: 451
    3rd October 2017, 18:31 Go to last post
  14. Running multiple program on flash

    Started by beginner_EDA, 2nd October 2017 13:28
    • Replies: 5
    • Views: 418
    2nd October 2017, 18:25 Go to last post
  15. problem by vivado in Rom Extraction from file !

    Started by Port Map, 2nd October 2017 11:50
    • Replies: 6
    • Views: 331
    2nd October 2017, 15:52 Go to last post
  16. Help in encrypting or obfuscation of a design!

    Started by Port Map, 29th September 2017 13:30
    • Replies: 6
    • Views: 792
    30th September 2017, 15:16 Go to last post
  17. Cyclone IV learning board

    Started by andrew_que, 8th August 2017 16:26
    • Replies: 4
    • Views: 731
    30th September 2017, 14:39 Go to last post
  18. Simple circuit not working.... VHDL

    Started by strange_steve, 29th September 2017 00:26
    • Replies: 8
    • Views: 824
    30th September 2017, 10:50 Go to last post
  19. Morton Scan or Z-Scan in vhdl

    Started by rafimiet, 28th September 2017 05:51
    • Replies: 3
    • Views: 433
    29th September 2017, 08:09 Go to last post
    • Replies: 1
    • Views: 379
    28th September 2017, 15:39 Go to last post
  20. testing a variable-length value

    Started by Binome, 27th September 2017 14:55
    • Replies: 5
    • Views: 547
    28th September 2017, 09:41 Go to last post
  21. synchronisation question

    Started by Binome, 27th September 2017 10:10
    • Replies: 5
    • Views: 437
    28th September 2017, 09:39 Go to last post
  22. I2C delay between SCL and SDA

    Started by manush30, 14th September 2017 15:44
    • Replies: 8
    • Views: 911
    27th September 2017, 10:04 Go to last post