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Threads 61 to 90 of 21681

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Reading and Writting to a RAM at the same time

    Started by srpronto, 30th May 2017 14:25
    • Replies: 3
    • Views: 249
    30th May 2017, 16:23 Go to last post
  2. [SOLVED] Crystal Oscillators instead of FPGA Clock

    Started by Kibos, 26th May 2017 13:41
    • Replies: 9
    • Views: 1,043
    30th May 2017, 14:58 Go to last post
    • Replies: 0
    • Views: 216
    28th May 2017, 17:41 Go to last post
  3. Reading a block RAM Xilinx IP Core

    Started by beginner_EDA, 26th May 2017 13:04
    • Replies: 3
    • Views: 362
    26th May 2017, 16:11 Go to last post
  4. creating axi slave peripheral in vivado ?

    Started by hcu, 25th May 2017 16:58
    • Replies: 3
    • Views: 310
    25th May 2017, 19:10 Go to last post
    • Replies: 7
    • Views: 431
    24th May 2017, 16:57 Go to last post
    • Replies: 10
    • Views: 788
    24th May 2017, 08:38 Go to last post
  5. SPI sample code using FPGA

    Started by myjoe1026, 22nd May 2017 07:14
    • Replies: 13
    • Views: 787
    24th May 2017, 04:02 Go to last post
    • Replies: 10
    • Views: 756
    23rd May 2017, 12:44 Go to last post
  6. i2c vhdl example code

    Started by amir_rch, 20th May 2017 13:14
    • Replies: 4
    • Views: 635
    22nd May 2017, 16:12 Go to last post
  7. B&R Automation Studio

    Started by sunshine2016, 12th May 2017 21:23
    • Replies: 3
    • Views: 377
    22nd May 2017, 16:09 Go to last post
  8. 128x64zw lcd interfacing with fpga

    Started by zacief, 16th May 2017 12:43
    • Replies: 10
    • Views: 692
    21st May 2017, 13:39 Go to last post
  9. Unable to infer RAM on Quartus Prime

    Started by FecP, 18th May 2017 17:00
    • Replies: 8
    • Views: 701
    20th May 2017, 09:29 Go to last post
  10. Working with a SPARTAN6 board

    Started by mahmood.n, 18th May 2017 12:26
    • Replies: 13
    • Views: 615
    20th May 2017, 08:24 Go to last post
  11. [SOLVED] verilog code for addition of contents in the memory

    Started by ecasha, 17th May 2017 18:35
    • Replies: 8
    • Views: 607
    19th May 2017, 06:46 Go to last post
  12. RPN Calculator using VHDL

    Started by NightOWL, 18th May 2017 20:30
    • Replies: 1
    • Views: 364
    19th May 2017, 00:23 Go to last post
  13. VHDL Design Problem Issues

    Started by dzafar, 15th May 2017 10:20
    • Replies: 14
    • Views: 721
    17th May 2017, 23:22 Go to last post
  14. 2 way communication between modules in VHDL

    Started by nizdom, 16th May 2017 15:10
    • Replies: 6
    • Views: 491
    17th May 2017, 16:26 Go to last post
  15. how to create matrix in VHDL

    Started by nizdom, 15th May 2017 15:46
    • Replies: 10
    • Views: 493
    17th May 2017, 13:13 Go to last post
    • Replies: 2
    • Views: 393
    17th May 2017, 06:03 Go to last post
  16. FPGA WARNING of initial value is never assigned

    Started by myjoe1026, 15th May 2017 10:39
    • Replies: 15
    • Views: 639
    17th May 2017, 04:38 Go to last post
    • Replies: 3
    • Views: 291
    17th May 2017, 03:54 Go to last post
  17. [SOLVED] Using numbers in if statement

    Started by salim.alam2, 16th May 2017 21:27
    • Replies: 5
    • Views: 264
    16th May 2017, 22:47 Go to last post
  18. What methods exist for division in FPGA

    Started by matrixofdynamism, 16th May 2017 15:51
    • Replies: 2
    • Views: 228
    16th May 2017, 21:08 Go to last post
    • Replies: 3
    • Views: 281
    16th May 2017, 16:10 Go to last post
    • Replies: 0
    • Views: 213
    16th May 2017, 15:45 Go to last post
  19. Signal Value from Multiple Processes

    Started by dzafar, 21st February 2017 16:23
    • Replies: 13
    • Views: 509
    16th May 2017, 08:12 Go to last post