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Threads 61 to 90 of 22009

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] concurrent vhdl code generating latches

    Started by rafimiet, 19th November 2017 10:10
    • Replies: 4
    • Views: 859
    19th November 2017, 11:43 Go to last post
  2. [moved] ZedBoard HDMI input without FMC card

    Started by DilshanSampath, 17th November 2017 18:13
    • Replies: 2
    • Views: 679
    18th November 2017, 20:02 Go to last post
  3. Moving window integrator

    Started by Rani1234, 17th November 2017 12:43
    • Replies: 4
    • Views: 594
    17th November 2017, 18:38 Go to last post
  4. [SOLVED] Initializing Xilinx BRAM with image pixels

    Started by Taki_comp, 6th November 2017 20:52
    • Replies: 10
    • Views: 1,328
    17th November 2017, 14:38 Go to last post
  5. FIR band pass filter using verilog

    Started by josephine1234, 17th November 2017 10:30
    • Replies: 6
    • Views: 551
    17th November 2017, 11:05 Go to last post
  6. Xilinx ISE - readmemh system task taking too much time

    Started by NikosTS, 14th November 2017 11:36
    • Replies: 1
    • Views: 475
    17th November 2017, 07:11 Go to last post
    • Replies: 1
    • Views: 623
    16th November 2017, 17:04 Go to last post
  7. VHDL coding techniques

    Started by manishpatkar, 13th November 2017 12:55
    • Replies: 16
    • Views: 1,303
    16th November 2017, 15:01 Go to last post
  8. Missing JESD parameters in Xilinx JESD204 IP Rx!!

    Started by samg, 15th November 2017 05:46
    • Replies: 2
    • Views: 558
    15th November 2017, 11:31 Go to last post
    • Replies: 5
    • Views: 745
    14th November 2017, 23:20 Go to last post
    • Replies: 1
    • Views: 382
    14th November 2017, 18:17 Go to last post
  9. Sending data sequentially

    Started by beginner_EDA, 8th November 2017 12:42
    • Replies: 6
    • Views: 703
    14th November 2017, 13:24 Go to last post
    • Replies: 3
    • Views: 967
    13th November 2017, 21:38 Go to last post
    • Replies: 3
    • Views: 1,323
    13th November 2017, 12:00 Go to last post
  10. Configuring JESD parameters in Xilinx JESD204

    Started by samg, 13th November 2017 07:01
    • Replies: 0
    • Views: 530
    13th November 2017, 07:01 Go to last post
    • Replies: 1
    • Views: 964
    11th November 2017, 13:03 Go to last post
  11. [SOLVED] Programmable Priority Encoder

    Started by RatedR, 13th July 2017 17:00
    2 Pages
    1 2
    • Replies: 31
    • Views: 3,853
    10th November 2017, 17:33 Go to last post
    • Replies: 12
    • Views: 1,507
    9th November 2017, 20:04 Go to last post
    • Replies: 1
    • Views: 439
    9th November 2017, 17:10 Go to last post
    • Replies: 3
    • Views: 581
    8th November 2017, 18:49 Go to last post
    • Replies: 2
    • Views: 394
    8th November 2017, 13:03 Go to last post
    • Replies: 14
    • Views: 1,855
    8th November 2017, 02:58 Go to last post
    • Replies: 3
    • Views: 456
    7th November 2017, 18:30 Go to last post
  12. LCD code for fpga virtex 6

    Started by moonshine8995, 6th November 2017 12:39
    • Replies: 3
    • Views: 686
    7th November 2017, 13:08 Go to last post
  13. Verilog basic coding/naming conventions

    Started by pigtwo, 4th November 2017 21:53
    • Replies: 7
    • Views: 878
    6th November 2017, 04:44 Go to last post
  14. [SOLVED] Latches create in verilog code

    Started by tayyab786, 3rd November 2017 06:03
    • Replies: 6
    • Views: 1,038
    5th November 2017, 16:47 Go to last post
  15. inout port in an inner component

    Started by rafimiet, 4th November 2017 06:07
    • Replies: 9
    • Views: 886
    5th November 2017, 00:32 Go to last post
    • Replies: 4
    • Views: 490
    3rd November 2017, 17:34 Go to last post
  16. Active HDL vs Models performance

    Started by shaiko, 3rd November 2017 15:45
    • Replies: 1
    • Views: 395
    3rd November 2017, 16:22 Go to last post
  17. Modelsim console configuration

    Started by wesleytaylor, 2nd November 2017 18:16
    • Replies: 0
    • Views: 596
    2nd November 2017, 18:16 Go to last post