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Threads 61 to 90 of 21555

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Ping pong buffer for DAQ IP

    Started by viyaaloth, 11th April 2017 09:47
    • Replies: 1
    • Views: 226
    11th April 2017, 12:11 Go to last post
  2. Verilog code to find pulsewidth

    Started by DeepikaUpendra, 10th April 2017 16:19
    • Replies: 1
    • Views: 190
    11th April 2017, 07:25 Go to last post
  3. Some advices in acurracy for a frequency counter using a spartan 6 fpga

    Started by moro, 8th April 2017 14:20
    2 Pages
    1 2
    • Replies: 23
    • Views: 521
    10th April 2017, 21:29 Go to last post
    • Replies: 5
    • Views: 222
    10th April 2017, 17:49 Go to last post
  4. Need old ISE version

    Started by 5arid, 8th April 2017 05:44
    • Replies: 3
    • Views: 275
    10th April 2017, 16:26 Go to last post
  5. [SOLVED] [moved] synthesis error RTL schematic

    Started by ecasha, 10th April 2017 15:11
    • Replies: 3
    • Views: 318
    10th April 2017, 16:02 Go to last post
  6. Using generic interfaces to program Lattice FPGA

    Started by whack, 9th April 2017 13:01
    • Replies: 2
    • Views: 208
    9th April 2017, 18:49 Go to last post
  7. Wishbone SSRAM Issue

    Started by DocJava, 8th April 2017 14:06
    • Replies: 3
    • Views: 242
    9th April 2017, 10:09 Go to last post
  8. Efficient SerDes-Like Module

    Started by SharpWeapon, 7th April 2017 04:01
    • Replies: 4
    • Views: 232
    9th April 2017, 02:35 Go to last post
  9. using fixed point design in vivado SDK

    Started by sai_shashi, 5th April 2017 06:06
    • Replies: 3
    • Views: 202
    8th April 2017, 08:49 Go to last post
    • Replies: 4
    • Views: 220
    8th April 2017, 06:22 Go to last post
  10. Understanding types of IO pins on FPGAs

    Started by whack, 7th April 2017 11:04
    • Replies: 7
    • Views: 210
    8th April 2017, 05:51 Go to last post
  11. Need help with generating *INTERLACED* mode VGA signals

    Started by whack, 22nd March 2017 06:06
    2 Pages
    1 2
    • Replies: 28
    • Views: 570
    8th April 2017, 05:22 Go to last post
  12. Problems writing Verilog testbench for 4:1 mux

    Started by pakha, 4th April 2017 21:25
    • Replies: 8
    • Views: 342
    8th April 2017, 00:35 Go to last post
  13. IP modules missing in Vivado testbench

    Started by MOd24, 1st April 2017 11:28
    • Replies: 3
    • Views: 191
    6th April 2017, 20:52 Go to last post
  14. Modelsim error scfifo of altera is not bound

    Started by sonika111, 5th April 2017 13:17
    • Replies: 6
    • Views: 238
    6th April 2017, 17:11 Go to last post
  15. Verilog Simple Spi Code

    Started by Mucit23, 5th April 2017 09:50
    • Replies: 5
    • Views: 270
    6th April 2017, 16:56 Go to last post
  16. Block RAM using IPcore

    Started by emerson_11, 6th April 2017 06:06
    • Replies: 1
    • Views: 198
    6th April 2017, 10:30 Go to last post
  17. Low speed bank Clock pins

    Started by rayhh27, 21st March 2017 11:28
    • Replies: 9
    • Views: 352
    6th April 2017, 09:54 Go to last post
  18. [SOLVED] How to connect my adc code to XILINX AXI4 FIR IP

    Started by tsillen, 4th April 2017 17:10
    • Replies: 14
    • Views: 333
    6th April 2017, 08:25 Go to last post
    • Replies: 2
    • Views: 128
    6th April 2017, 07:46 Go to last post
    • Replies: 3
    • Views: 182
    5th April 2017, 17:12 Go to last post
  19. cordic for inverse trigonometry

    Started by reshmacv76, 30th March 2017 05:32
    • Replies: 5
    • Views: 237
    5th April 2017, 08:10 Go to last post
    • Replies: 0
    • Views: 118
    5th April 2017, 07:29 Go to last post
  20. Navigation through a path in Vivado

    Started by msdarvishi, 4th April 2017 20:58
    • Replies: 4
    • Views: 162
    5th April 2017, 00:43 Go to last post
    • Replies: 1
    • Views: 153
    4th April 2017, 14:49 Go to last post
  21. Stateless Module in HDL design

    Started by viyaaloth, 4th April 2017 10:34
    • Replies: 2
    • Views: 148
    4th April 2017, 11:09 Go to last post
    • Replies: 0
    • Views: 159
    4th April 2017, 06:14 Go to last post