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Threads 61 to 90 of 21880

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Initializing a very long vector with some repetition

    Started by rafimiet, 12th September 2017 12:59
    • Replies: 8
    • Views: 523
    13th September 2017, 09:28 Go to last post
  2. Cyclone ii fpga flash memory erasing

    Started by hareeshP, 12th September 2017 09:33
    • Replies: 8
    • Views: 548
    13th September 2017, 06:03 Go to last post
  3. word's length of single port RAM

    Started by tanish, 12th September 2017 14:24
    • Replies: 5
    • Views: 408
    13th September 2017, 00:28 Go to last post
    • Replies: 7
    • Views: 378
    12th September 2017, 10:44 Go to last post
  4. Solving hold time problems via SDC only

    Started by shaiko, 10th September 2017 12:04
    • Replies: 8
    • Views: 714
    12th September 2017, 09:12 Go to last post
    • Replies: 6
    • Views: 557
    12th September 2017, 05:20 Go to last post
  5. Using a buffer to modify an input port

    Started by mahmood.n, 11th September 2017 15:54
    • Replies: 11
    • Views: 463
    11th September 2017, 22:05 Go to last post
  6. [SOLVED] ERROR:HDLParsers:3375

    Started by rafimiet, 11th September 2017 18:04
    • Replies: 1
    • Views: 279
    11th September 2017, 18:57 Go to last post
  7. Better performance measure LUT vs FF

    Started by SharpWeapon, 9th September 2017 14:30
    • Replies: 6
    • Views: 447
    11th September 2017, 18:08 Go to last post
  8. Accessing range of array elements VHDL

    Started by Curios_Eng, 11th September 2017 11:53
    • Replies: 2
    • Views: 289
    11th September 2017, 16:46 Go to last post
  9. simulation in vivado vs ISIM(in Xilinx ISE)

    Started by rafimiet, 10th September 2017 05:30
    • Replies: 3
    • Views: 392
    11th September 2017, 13:12 Go to last post
  10. Run all Vivado synthesis strategies in one run

    Started by SharpWeapon, 9th September 2017 14:25
    • Replies: 1
    • Views: 272
    11th September 2017, 09:24 Go to last post
  11. Avalon BFM burst operation.

    Started by muthu7495, 11th September 2017 08:07
    • Replies: 0
    • Views: 235
    11th September 2017, 08:07 Go to last post
  12. [SOLVED] how to locate the addresses of 1's in std_logic_vector

    Started by rafimiet, 9th September 2017 05:19
    • Replies: 12
    • Views: 546
    10th September 2017, 19:33 Go to last post
  13. [SOLVED] Difference between combinational path delay and minimum period

    Started by rafimiet, 10th September 2017 06:56
    • Replies: 3
    • Views: 333
    10th September 2017, 14:31 Go to last post
  14. FMC Daughter card info

    Started by sreedharvictor, 10th September 2017 11:17
    • Replies: 1
    • Views: 220
    10th September 2017, 11:35 Go to last post
  15. [SOLVED] radix 4 booth multiplier using 3:2 CSA

    Started by virat_gupta, 9th September 2017 10:03
    • Replies: 0
    • Views: 176
    9th September 2017, 10:03 Go to last post
  16. verilog code for creating and deleting of clock error.

    Started by ashok12, 8th September 2017 11:20
    • Replies: 5
    • Views: 360
    9th September 2017, 07:18 Go to last post
    • Replies: 0
    • Views: 206
    8th September 2017, 22:42 Go to last post
  17. Shift register will parallel load

    Started by sandy2811, 5th September 2017 13:17
    • Replies: 3
    • Views: 392
    8th September 2017, 15:26 Go to last post
  18. convert Floating point to fix point

    Started by linam, 7th September 2017 10:06
    • Replies: 6
    • Views: 395
    8th September 2017, 11:49 Go to last post
    • Replies: 1
    • Views: 199
    7th September 2017, 16:43 Go to last post
  19. very strange typecast (VHDL)

    Started by LatticeSemiconductor, 28th August 2017 10:57
    • Replies: 5
    • Views: 435
    7th September 2017, 13:13 Go to last post
  20. Counter Preload by any given values

    Started by sandy2811, 1st September 2017 07:55
    • Replies: 12
    • Views: 884
    7th September 2017, 06:12 Go to last post
  21. Strange behaviour of Standard dual-clock FIFO

    Started by Taki_comp, 3rd September 2017 14:19
    • Replies: 10
    • Views: 471
    4th September 2017, 08:18 Go to last post
  22. problem with VHDL mealy sequence detector

    Started by Armand86, 1st September 2017 21:47
    • Replies: 7
    • Views: 452
    2nd September 2017, 19:33 Go to last post
  23. How to design self checking testbench...

    Started by sandy2811, 22nd August 2017 13:10
    • Replies: 3
    • Views: 527
    2nd September 2017, 04:33 Go to last post
  24. Measuring the execution time on FPGA

    Started by doost4, 26th August 2017 18:39
    2 Pages
    1 2
    • Replies: 23
    • Views: 1,134
    30th August 2017, 16:12 Go to last post
  25. Moved: Programmable Priority Encoder

    Started by RatedR, 29th August 2017 15:55
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