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Threads 61 to 90 of 21778

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 3
    • Views: 470
    18th July 2017, 19:00 Go to last post
  1. Multicast address in 10 Gig Ethernet IP

    Started by beginner_EDA, 18th July 2017 14:00
    • Replies: 3
    • Views: 284
    18th July 2017, 15:06 Go to last post
  2. VHDL array comparison

    Started by Telboy99, 16th July 2017 12:35
    • Replies: 3
    • Views: 485
    17th July 2017, 13:31 Go to last post
  3. ADC with Qsys tool Altera

    Started by grezzoman, 3rd July 2017 15:30
    • Replies: 2
    • Views: 420
    16th July 2017, 23:53 Go to last post
  4. Monolithic vs non-Monolithic FPGA

    Started by shaiko, 14th July 2017 13:58
    • Replies: 7
    • Views: 478
    15th July 2017, 00:06 Go to last post
    • Replies: 1
    • Views: 313
    14th July 2017, 07:06 Go to last post
  5. TimeQuest analysis for pulse width

    Started by mahmood.n, 13th July 2017 11:18
    • Replies: 1
    • Views: 486
    13th July 2017, 19:11 Go to last post
  6. question about CMT of the spartan 6

    Started by matin-kh, 12th July 2017 12:20
    • Replies: 1
    • Views: 440
    13th July 2017, 02:24 Go to last post
  7. What FPGA logic do constants consume

    Started by shaiko, 11th July 2017 22:20
    • Replies: 7
    • Views: 768
    12th July 2017, 17:13 Go to last post
  8. Strange simulator behavior for code in Verilog

    Started by Gizmotoy, 10th July 2017 23:34
    • Replies: 9
    • Views: 667
    11th July 2017, 22:21 Go to last post
    • Replies: 14
    • Views: 1,025
    11th July 2017, 17:56 Go to last post
  9. Implementing Look up table in FPGA

    Started by beginner_EDA, 5th July 2017 15:55
    • Replies: 13
    • Views: 844
    11th July 2017, 13:51 Go to last post
  10. Synthesis: Check_Design Report too many warnings

    Started by Johannah, 13th June 2017 08:48
    • Replies: 6
    • Views: 826
    11th July 2017, 08:40 Go to last post
    • Replies: 2
    • Views: 302
    10th July 2017, 18:21 Go to last post
  11. signal value conflict in VHDL

    Started by mahmood.n, 9th July 2017 12:03
    • Replies: 16
    • Views: 879
    10th July 2017, 16:49 Go to last post
  12. Difference b/w asynchronous Vs synchronous FIFO

    Started by rac70, 7th July 2017 12:53
    • Replies: 5
    • Views: 430
    10th July 2017, 10:39 Go to last post
  13. getting and passing data in CPLD

    Started by linam, 7th July 2017 09:38
    • Replies: 3
    • Views: 588
    9th July 2017, 10:36 Go to last post
  14. PCIe-PCI bridge Soft IP core in FPGA

    Started by fpga93, 7th July 2017 10:23
    • Replies: 0
    • Views: 251
    7th July 2017, 10:23 Go to last post
  15. Proper 10-bit 100mhz parallel ADC interface

    Started by asdf44, 7th July 2017 01:55
    • Replies: 3
    • Views: 422
    7th July 2017, 06:59 Go to last post
    • Replies: 6
    • Views: 506
    6th July 2017, 19:06 Go to last post
    • Replies: 0
    • Views: 247
    6th July 2017, 14:29 Go to last post
  16. JTAG pin constarints in VC707

    Started by prakashgudala, 6th July 2017 10:59
    • Replies: 1
    • Views: 234
    6th July 2017, 14:24 Go to last post
  17. [SOLVED] Unable to understand timing diagram of a digital ckt

    Started by hobbyiclearner, 5th July 2017 10:11
    • Replies: 8
    • Views: 447
    6th July 2017, 11:20 Go to last post
  18. How to avoid using clock trees in Zynq FPGAs?

    Started by msdarvishi, 15th June 2017 00:35
    • Replies: 7
    • Views: 903
    6th July 2017, 04:48 Go to last post
    • Replies: 1
    • Views: 350
    6th July 2017, 00:59 Go to last post
  19. matrix array from instantiations

    Started by nizdom, 21st June 2017 10:33
    • Replies: 7
    • Views: 582
    5th July 2017, 22:51 Go to last post