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Threads 61 to 90 of 21963

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Multiplexer in VHDL with a 2D array and for loop

    Started by moonshine8995, 27th October 2017 12:37
    • Replies: 3
    • Views: 302
    27th October 2017, 15:19 Go to last post
  2. 10 Gig ethernet Packet capture tool

    Started by beginner_EDA, 27th October 2017 12:03
    • Replies: 1
    • Views: 270
    27th October 2017, 12:48 Go to last post
  3. Convert std_logic_vector to integer

    Started by moonshine8995, 26th October 2017 13:05
    • Replies: 7
    • Views: 407
    27th October 2017, 12:11 Go to last post
  4. Problem to understand internal architecture of JTAG

    Started by sandy2811, 25th October 2017 05:43
    • Replies: 7
    • Views: 738
    27th October 2017, 11:02 Go to last post
  5. Function 'test' could not be resolved in HLS

    Started by mouhamedmb, 27th October 2017 10:23
    • Replies: 0
    • Views: 202
    27th October 2017, 10:23 Go to last post
  6. [SOLVED] System Verilog error in modelsim with enum types.

    Started by vipinlal, 26th October 2017 15:06
    • Replies: 3
    • Views: 286
    26th October 2017, 16:52 Go to last post
  7. Interfacing a VGA port with a PLD

    Started by garvind25, 25th October 2017 07:16
    • Replies: 7
    • Views: 565
    26th October 2017, 11:24 Go to last post
    • Replies: 1
    • Views: 357
    26th October 2017, 09:28 Go to last post
  8. [SOLVED] Need adpll , vhdl basics sources

    Started by manishpatkar, 25th October 2017 17:39
    • Replies: 1
    • Views: 343
    25th October 2017, 18:45 Go to last post
  9. Help me to write verilog code

    Started by sugubai, 25th October 2017 11:52
    • Replies: 5
    • Views: 370
    25th October 2017, 16:23 Go to last post
  10. Cyclone 5 sockit usb_uart port

    Started by dipin, 30th September 2017 10:47
    • Replies: 7
    • Views: 753
    25th October 2017, 12:10 Go to last post
  11. Moved: sending 64 bits from fpga to pc using hps @10khz

    Started by dipin, 25th October 2017 15:32
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  12. [moved] How to clear Verilog HDL error

    Started by sugubai, 22nd October 2017 05:57
    • Replies: 7
    • Views: 674
    25th October 2017, 11:55 Go to last post
    • Replies: 0
    • Views: 237
    24th October 2017, 23:08 Go to last post
  13. How to update flash with user logic?

    Started by bravoegg, 24th October 2017 13:27
    • Replies: 4
    • Views: 286
    24th October 2017, 17:11 Go to last post
    • Replies: 6
    • Views: 552
    24th October 2017, 16:14 Go to last post
    • Replies: 2
    • Views: 286
    24th October 2017, 14:42 Go to last post
  14. Waveform of verilog "reg" inside a task in Vivado

    Started by samg, 24th October 2017 11:00
    • Replies: 0
    • Views: 183
    24th October 2017, 11:00 Go to last post
  15. [SOLVED] Register space addressing in Xilinx JESD204

    Started by samg, 24th October 2017 05:22
    • Replies: 1
    • Views: 285
    24th October 2017, 08:41 Go to last post
  16. [SOLVED] Using BRAM by infering and by using IP

    Started by rafimiet, 23rd October 2017 08:05
    • Replies: 10
    • Views: 445
    23rd October 2017, 22:19 Go to last post
  17. MAX II CPLD performance

    Started by hareeshP, 23rd October 2017 11:09
    • Replies: 1
    • Views: 241
    23rd October 2017, 11:33 Go to last post
  18. [SOLVED] Two True-Dual-port rams in Zedboard

    Started by rafimiet, 21st October 2017 07:34
    • Replies: 3
    • Views: 354
    21st October 2017, 10:48 Go to last post
    • Replies: 10
    • Views: 620
    19th October 2017, 22:23 Go to last post
  19. Problem facing in Xpower Analyzer

    Started by qaziarbab, 12th October 2017 16:01
    • Replies: 7
    • Views: 625
    19th October 2017, 13:10 Go to last post
    • Replies: 18
    • Views: 1,133
    18th October 2017, 18:35 Go to last post
  20. Configuring JESD parameters in Xilinx JESD204 IP

    Started by samg, 18th October 2017 06:04
    • Replies: 0
    • Views: 327
    18th October 2017, 06:04 Go to last post
  21. Generate vhdl netlist by ise

    Started by moonshine8995, 14th October 2017 17:42
    • Replies: 4
    • Views: 620
    16th October 2017, 09:47 Go to last post
  22. Intialization of SDRAM DDR2 memory in Xilinx tools

    Started by Taki_comp, 13th October 2017 12:12
    • Replies: 6
    • Views: 629
    15th October 2017, 16:01 Go to last post
  23. Verilog Syntax error

    Started by hansben, 14th October 2017 05:16
    • Replies: 1
    • Views: 442
    14th October 2017, 07:43 Go to last post