1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    95,066
Page 3 of 728 FirstFirst 1 2 3 4 5 13 53 103 503 ... LastLast
Threads 61 to 90 of 21840

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 12
    • Views: 1,274
    23rd August 2017, 23:24 Go to last post
  1. Spartan - 3A ADC and DAC interface not working

    Started by NJ176, 15th August 2017 10:22
    • Replies: 8
    • Views: 572
    23rd August 2017, 19:14 Go to last post
  2. [SOLVED] Tcl to update version number

    Started by wesleytaylor, 18th August 2017 13:04
    • Replies: 6
    • Views: 582
    23rd August 2017, 16:33 Go to last post
  3. Cadence NCSIM Document

    Started by muthu7495, 22nd August 2017 13:04
    • Replies: 2
    • Views: 398
    22nd August 2017, 15:17 Go to last post
    • Replies: 1
    • Views: 336
    22nd August 2017, 13:29 Go to last post
  4. SuperCap in Xilinx Zynq

    Started by flote21, 22nd August 2017 07:35
    • Replies: 1
    • Views: 376
    22nd August 2017, 10:34 Go to last post
  5. Avery AXI_SLAVE warning

    Started by muthu7495, 21st August 2017 10:57
    • Replies: 3
    • Views: 359
    21st August 2017, 14:52 Go to last post
  6. FPGA asic design tools

    Started by flo, 19th August 2017 20:28
    • Replies: 3
    • Views: 651
    20th August 2017, 13:25 Go to last post
  7. High Level employment of the "imply" operator

    Started by BrownBear1968, 17th August 2017 21:55
    • Replies: 6
    • Views: 887
    18th August 2017, 22:32 Go to last post
  8. saving the the content of a nios2 console.

    Started by dipin, 17th August 2017 10:06
    • Replies: 0
    • Views: 378
    17th August 2017, 10:06 Go to last post
    • Replies: 3
    • Views: 595
    16th August 2017, 11:31 Go to last post
    • Replies: 5
    • Views: 411
    15th August 2017, 19:39 Go to last post
  9. a logic to detect FPGA family?

    Started by Port Map, 13th August 2017 10:42
    • Replies: 8
    • Views: 575
    15th August 2017, 09:31 Go to last post
  10. synchronize data with general GPIO clk

    Started by nsgil85, 13th August 2017 11:27
    • Replies: 8
    • Views: 582
    14th August 2017, 15:59 Go to last post
    • Replies: 5
    • Views: 606
    12th August 2017, 20:54 Go to last post
    • Replies: 5
    • Views: 411
    12th August 2017, 13:59 Go to last post
  11. How to snyc one 7 Series Transceiver to anothe

    Started by beginner_EDA, 11th August 2017 13:42
    • Replies: 3
    • Views: 400
    12th August 2017, 09:32 Go to last post
  12. how to fix WARNING:Xst:1710

    Started by tanish, 12th August 2017 08:07
    • Replies: 1
    • Views: 288
    12th August 2017, 08:42 Go to last post
  13. optimized CDR settings for 12G-SDI

    Started by beginner_EDA, 10th August 2017 09:58
    • Replies: 1
    • Views: 360
    11th August 2017, 15:56 Go to last post
  14. VHDL Instantiation in modelSim

    Started by hareeshP, 10th August 2017 06:57
    • Replies: 14
    • Views: 689
    10th August 2017, 19:16 Go to last post
  15. Cannot Read Data in 1-Port RAM IP Core

    Started by learni, 10th August 2017 09:40
    • Replies: 2
    • Views: 533
    10th August 2017, 18:52 Go to last post
  16. ADC and DAC interface for Spartan - 3A

    Started by NJ176, 10th August 2017 11:02
    • Replies: 1
    • Views: 294
    10th August 2017, 13:13 Go to last post
  17. Cyclone IV learning board

    Started by andrew_que, 8th August 2017 16:26
    • Replies: 3
    • Views: 494
    9th August 2017, 11:33 Go to last post
    • Replies: 10
    • Views: 964
    9th August 2017, 06:27 Go to last post
  18. Same constant name in 2 different packages

    Started by shaiko, 5th August 2017 12:53
    • Replies: 11
    • Views: 1,049
    7th August 2017, 10:23 Go to last post
  19. FPGA timing due to Dist ram

    Started by Alauddin123, 6th August 2017 10:42
    • Replies: 1
    • Views: 426
    6th August 2017, 12:08 Go to last post
  20. use C to program FPGA

    Started by matin-kh, 2nd July 2017 12:39
    • Replies: 11
    • Views: 1,902
    4th August 2017, 23:04 Go to last post
  21. substitution for loops in design compiler

    Started by moonshine8995, 4th August 2017 11:04
    • Replies: 4
    • Views: 668
    4th August 2017, 18:02 Go to last post
  22. Amp ADC interfacing using VHDL for Spartan-3A

    Started by NJ176, 31st July 2017 09:44
    • Replies: 4
    • Views: 809
    4th August 2017, 17:49 Go to last post
  23. [SOLVED] xilinx timing analyze using modelsim SE

    Started by tanish, 3rd August 2017 17:53
    • Replies: 1
    • Views: 611
    3rd August 2017, 20:53 Go to last post