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Threads 61 to 90 of 21957

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Interfacing a VGA port with a PLD

    Started by garvind25, 25th October 2017 07:16
    • Replies: 7
    • Views: 523
    26th October 2017, 11:24 Go to last post
    • Replies: 1
    • Views: 344
    26th October 2017, 09:28 Go to last post
  2. [SOLVED] Need adpll , vhdl basics sources

    Started by manishpatkar, 25th October 2017 17:39
    • Replies: 1
    • Views: 335
    25th October 2017, 18:45 Go to last post
  3. Help me to write verilog code

    Started by sugubai, 25th October 2017 11:52
    • Replies: 5
    • Views: 360
    25th October 2017, 16:23 Go to last post
  4. Cyclone 5 sockit usb_uart port

    Started by dipin, 30th September 2017 10:47
    • Replies: 7
    • Views: 747
    25th October 2017, 12:10 Go to last post
  5. Moved: sending 64 bits from fpga to pc using hps @10khz

    Started by dipin, 25th October 2017 15:32
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  6. [moved] How to clear Verilog HDL error

    Started by sugubai, 22nd October 2017 05:57
    • Replies: 7
    • Views: 661
    25th October 2017, 11:55 Go to last post
    • Replies: 0
    • Views: 235
    24th October 2017, 23:08 Go to last post
  7. How to update flash with user logic?

    Started by bravoegg, 24th October 2017 13:27
    • Replies: 4
    • Views: 285
    24th October 2017, 17:11 Go to last post
    • Replies: 6
    • Views: 537
    24th October 2017, 16:14 Go to last post
    • Replies: 2
    • Views: 285
    24th October 2017, 14:42 Go to last post
  8. Waveform of verilog "reg" inside a task in Vivado

    Started by samg, 24th October 2017 11:00
    • Replies: 0
    • Views: 174
    24th October 2017, 11:00 Go to last post
  9. [SOLVED] Register space addressing in Xilinx JESD204

    Started by samg, 24th October 2017 05:22
    • Replies: 1
    • Views: 277
    24th October 2017, 08:41 Go to last post
  10. [SOLVED] Using BRAM by infering and by using IP

    Started by rafimiet, 23rd October 2017 08:05
    • Replies: 10
    • Views: 429
    23rd October 2017, 22:19 Go to last post
  11. MAX II CPLD performance

    Started by hareeshP, 23rd October 2017 11:09
    • Replies: 1
    • Views: 238
    23rd October 2017, 11:33 Go to last post
  12. [SOLVED] Two True-Dual-port rams in Zedboard

    Started by rafimiet, 21st October 2017 07:34
    • Replies: 3
    • Views: 349
    21st October 2017, 10:48 Go to last post
    • Replies: 10
    • Views: 612
    19th October 2017, 22:23 Go to last post
  13. Problem facing in Xpower Analyzer

    Started by qaziarbab, 12th October 2017 16:01
    • Replies: 7
    • Views: 616
    19th October 2017, 13:10 Go to last post
    • Replies: 18
    • Views: 1,130
    18th October 2017, 18:35 Go to last post
  14. Configuring JESD parameters in Xilinx JESD204 IP

    Started by samg, 18th October 2017 06:04
    • Replies: 0
    • Views: 326
    18th October 2017, 06:04 Go to last post
  15. Generate vhdl netlist by ise

    Started by moonshine8995, 14th October 2017 17:42
    • Replies: 4
    • Views: 610
    16th October 2017, 09:47 Go to last post
  16. Intialization of SDRAM DDR2 memory in Xilinx tools

    Started by Taki_comp, 13th October 2017 12:12
    • Replies: 6
    • Views: 624
    15th October 2017, 16:01 Go to last post
  17. Verilog Syntax error

    Started by hansben, 14th October 2017 05:16
    • Replies: 1
    • Views: 440
    14th October 2017, 07:43 Go to last post
    • Replies: 2
    • Views: 356
    12th October 2017, 14:13 Go to last post
    • Replies: 1
    • Views: 420
    12th October 2017, 02:30 Go to last post
  18. Inequality operator in VHDL

    Started by nizdom, 11th October 2017 10:56
    • Replies: 2
    • Views: 353
    11th October 2017, 11:31 Go to last post
    • Replies: 4
    • Views: 482
    11th October 2017, 07:31 Go to last post
  19. Regarding connections in a CPLD schematic

    Started by garvind25, 10th October 2017 12:19
    • Replies: 6
    • Views: 464
    11th October 2017, 06:51 Go to last post