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Threads 61 to 90 of 22012

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. MachXO2 DDR and PCLK routing issue

    Started by juanMco, 20th November 2017 17:32
    • Replies: 4
    • Views: 887
    21st November 2017, 17:48 Go to last post
  2. MAX10 PLL External Clock Output

    Started by Yorki, 9th November 2017 14:35
    • Replies: 7
    • Views: 963
    21st November 2017, 09:55 Go to last post
  3. FPGA interface with 100Mbps Ethernet

    Started by fouwad, 17th November 2017 07:10
    • Replies: 3
    • Views: 1,204
    20th November 2017, 14:26 Go to last post
  4. Help tracking down very long synthesis time

    Started by whaleeee, 13th November 2017 19:51
    • Replies: 13
    • Views: 1,611
    20th November 2017, 08:48 Go to last post
  5. [SOLVED] concurrent vhdl code generating latches

    Started by rafimiet, 19th November 2017 10:10
    • Replies: 4
    • Views: 864
    19th November 2017, 11:43 Go to last post
  6. [moved] ZedBoard HDMI input without FMC card

    Started by DilshanSampath, 17th November 2017 18:13
    • Replies: 2
    • Views: 682
    18th November 2017, 20:02 Go to last post
  7. Moving window integrator

    Started by Rani1234, 17th November 2017 12:43
    • Replies: 4
    • Views: 599
    17th November 2017, 18:38 Go to last post
  8. [SOLVED] Initializing Xilinx BRAM with image pixels

    Started by Taki_comp, 6th November 2017 20:52
    • Replies: 10
    • Views: 1,333
    17th November 2017, 14:38 Go to last post
  9. FIR band pass filter using verilog

    Started by josephine1234, 17th November 2017 10:30
    • Replies: 6
    • Views: 555
    17th November 2017, 11:05 Go to last post
  10. Xilinx ISE - readmemh system task taking too much time

    Started by NikosTS, 14th November 2017 11:36
    • Replies: 1
    • Views: 478
    17th November 2017, 07:11 Go to last post
    • Replies: 1
    • Views: 627
    16th November 2017, 17:04 Go to last post
  11. VHDL coding techniques

    Started by manishpatkar, 13th November 2017 12:55
    • Replies: 16
    • Views: 1,311
    16th November 2017, 15:01 Go to last post
  12. Missing JESD parameters in Xilinx JESD204 IP Rx!!

    Started by samg, 15th November 2017 05:46
    • Replies: 2
    • Views: 561
    15th November 2017, 11:31 Go to last post
    • Replies: 5
    • Views: 747
    14th November 2017, 23:20 Go to last post
    • Replies: 1
    • Views: 385
    14th November 2017, 18:17 Go to last post
  13. Sending data sequentially

    Started by beginner_EDA, 8th November 2017 12:42
    • Replies: 6
    • Views: 706
    14th November 2017, 13:24 Go to last post
    • Replies: 3
    • Views: 971
    13th November 2017, 21:38 Go to last post
    • Replies: 3
    • Views: 1,326
    13th November 2017, 12:00 Go to last post
  14. Configuring JESD parameters in Xilinx JESD204

    Started by samg, 13th November 2017 07:01
    • Replies: 0
    • Views: 532
    13th November 2017, 07:01 Go to last post
    • Replies: 1
    • Views: 969
    11th November 2017, 13:03 Go to last post
  15. [SOLVED] Programmable Priority Encoder

    Started by RatedR, 13th July 2017 17:00
    2 Pages
    1 2
    • Replies: 31
    • Views: 3,862
    10th November 2017, 17:33 Go to last post
    • Replies: 12
    • Views: 1,511
    9th November 2017, 20:04 Go to last post
    • Replies: 1
    • Views: 442
    9th November 2017, 17:10 Go to last post
    • Replies: 3
    • Views: 585
    8th November 2017, 18:49 Go to last post
    • Replies: 2
    • Views: 395
    8th November 2017, 13:03 Go to last post
    • Replies: 14
    • Views: 1,861
    8th November 2017, 02:58 Go to last post
    • Replies: 3
    • Views: 459
    7th November 2017, 18:30 Go to last post
  16. LCD code for fpga virtex 6

    Started by moonshine8995, 6th November 2017 12:39
    • Replies: 3
    • Views: 706
    7th November 2017, 13:08 Go to last post
  17. Verilog basic coding/naming conventions

    Started by pigtwo, 4th November 2017 21:53
    • Replies: 7
    • Views: 883
    6th November 2017, 04:44 Go to last post
  18. [SOLVED] Latches create in verilog code

    Started by tayyab786, 3rd November 2017 06:03
    • Replies: 6
    • Views: 1,044
    5th November 2017, 16:47 Go to last post