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Threads 61 to 90 of 22100

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 4
    • Views: 474
    15th January 2018, 09:27 Go to last post
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    12th January 2018, 20:00 Go to last post
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    12th January 2018, 14:32 Go to last post
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    12th January 2018, 07:29 Go to last post
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    10th January 2018, 20:30 Go to last post
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    10th January 2018, 14:20 Go to last post
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    10th January 2018, 12:35 Go to last post
  1. [SOLVED] irrational clk period

    Started by nsgil85, 31st December 2017 08:59
    2 Pages
    1 2
    • Replies: 26
    • Views: 1,316
    8th January 2018, 17:00 Go to last post
  2. QPSK Modulator Design Issues

    Started by NichollsGlen, 28th December 2017 03:39
    • Replies: 2
    • Views: 524
    8th January 2018, 02:44 Go to last post
  3. [Altera] altera_mf lib -> how to compile/map?

    Started by ivlsi, 7th January 2018 02:53
    • Replies: 0
    • Views: 329
    7th January 2018, 02:53 Go to last post
  4. What is the Total Negative Slack

    Started by Serwan Bamerni, 6th January 2018 00:27
    • Replies: 4
    • Views: 525
    6th January 2018, 16:17 Go to last post
  5. How to get real time instances of an ecg signal

    Started by josephine1234, 5th January 2018 13:39
    • Replies: 4
    • Views: 402
    5th January 2018, 15:18 Go to last post
  6. Advice on configuring vim & syntastic for vhdl

    Started by wesleytaylor, 5th January 2018 10:23
    • Replies: 0
    • Views: 303
    5th January 2018, 10:23 Go to last post
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    • Views: 472
    4th January 2018, 09:17 Go to last post
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    • Views: 337
    3rd January 2018, 18:37 Go to last post
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    • Views: 534
    3rd January 2018, 15:19 Go to last post
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    • Views: 356
    3rd January 2018, 14:34 Go to last post
  7. Asynchronous pulse counter on fpga

    Started by shahulakthar, 26th December 2017 05:44
    • Replies: 10
    • Views: 877
    3rd January 2018, 00:28 Go to last post
  8. Generating multiple HDMI outputs with FPGA

    Started by francolomb, 1st January 2018 15:26
    • Replies: 4
    • Views: 482
    2nd January 2018, 13:48 Go to last post
  9. [SOLVED] Power Vs Area utilization in an FPGA

    Started by rafimiet, 28th December 2017 06:26
    • Replies: 8
    • Views: 662
    30th December 2017, 15:23 Go to last post
  10. SignalTap waiting for clock

    Started by hareeshP, 28th December 2017 10:33
    • Replies: 5
    • Views: 514
    29th December 2017, 10:39 Go to last post
  11. Need code for reference

    Started by Merlin10, 28th December 2017 19:10
    • Replies: 0
    • Views: 363
    28th December 2017, 19:10 Go to last post
  12. Direct memory access through VDMA and DMA

    Started by DilshanSampath, 28th December 2017 16:32
    • Replies: 0
    • Views: 343
    28th December 2017, 16:32 Go to last post
  13. Altera Stratix 10 Hyper-Registers

    Started by Wiljan, 9th December 2017 14:24
    • Replies: 9
    • Views: 1,108
    26th December 2017, 12:12 Go to last post
    • Replies: 1
    • Views: 312
    26th December 2017, 11:17 Go to last post
  14. [SOLVED] Simulation time in simulation tools like ISIM/model sim

    Started by mjuneja, 5th December 2017 08:25
    • Replies: 6
    • Views: 1,020
    26th December 2017, 06:59 Go to last post
  15. [SOLVED] Low speed on hps to fpga bridge

    Started by dipin, 23rd December 2017 15:57
    • Replies: 2
    • Views: 509
    24th December 2017, 14:09 Go to last post
    • Replies: 0
    • Views: 351
    23rd December 2017, 11:14 Go to last post
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    • Views: 515
    23rd December 2017, 07:57 Go to last post