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Threads 61 to 90 of 22001

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Missing JESD parameters in Xilinx JESD204 IP Rx!!

    Started by samg, 15th November 2017 05:46
    • Replies: 2
    • Views: 554
    15th November 2017, 11:31 Go to last post
    • Replies: 5
    • Views: 741
    14th November 2017, 23:20 Go to last post
    • Replies: 1
    • Views: 379
    14th November 2017, 18:17 Go to last post
  2. Sending data sequentially

    Started by beginner_EDA, 8th November 2017 12:42
    • Replies: 6
    • Views: 700
    14th November 2017, 13:24 Go to last post
    • Replies: 3
    • Views: 960
    13th November 2017, 21:38 Go to last post
    • Replies: 3
    • Views: 1,290
    13th November 2017, 12:00 Go to last post
  3. Configuring JESD parameters in Xilinx JESD204

    Started by samg, 13th November 2017 07:01
    • Replies: 0
    • Views: 526
    13th November 2017, 07:01 Go to last post
    • Replies: 1
    • Views: 952
    11th November 2017, 13:03 Go to last post
  4. [SOLVED] Programmable Priority Encoder

    Started by RatedR, 13th July 2017 17:00
    2 Pages
    1 2
    • Replies: 31
    • Views: 3,832
    10th November 2017, 17:33 Go to last post
    • Replies: 12
    • Views: 1,496
    9th November 2017, 20:04 Go to last post
    • Replies: 1
    • Views: 431
    9th November 2017, 17:10 Go to last post
    • Replies: 3
    • Views: 577
    8th November 2017, 18:49 Go to last post
    • Replies: 2
    • Views: 391
    8th November 2017, 13:03 Go to last post
    • Replies: 14
    • Views: 1,845
    8th November 2017, 02:58 Go to last post
    • Replies: 3
    • Views: 454
    7th November 2017, 18:30 Go to last post
  5. LCD code for fpga virtex 6

    Started by moonshine8995, 6th November 2017 12:39
    • Replies: 3
    • Views: 677
    7th November 2017, 13:08 Go to last post
  6. Verilog basic coding/naming conventions

    Started by pigtwo, 4th November 2017 21:53
    • Replies: 7
    • Views: 876
    6th November 2017, 04:44 Go to last post
  7. [SOLVED] Latches create in verilog code

    Started by tayyab786, 3rd November 2017 06:03
    • Replies: 6
    • Views: 1,033
    5th November 2017, 16:47 Go to last post
  8. inout port in an inner component

    Started by rafimiet, 4th November 2017 06:07
    • Replies: 9
    • Views: 882
    5th November 2017, 00:32 Go to last post
    • Replies: 4
    • Views: 489
    3rd November 2017, 17:34 Go to last post
  9. Active HDL vs Models performance

    Started by shaiko, 3rd November 2017 15:45
    • Replies: 1
    • Views: 392
    3rd November 2017, 16:22 Go to last post
  10. Modelsim console configuration

    Started by wesleytaylor, 2nd November 2017 18:16
    • Replies: 0
    • Views: 593
    2nd November 2017, 18:16 Go to last post
  11. [SOLVED] VHDL - Unknown identify

    Started by wesleytaylor, 30th October 2017 12:13
    • Replies: 4
    • Views: 572
    2nd November 2017, 00:08 Go to last post
    • Replies: 3
    • Views: 687
    1st November 2017, 19:08 Go to last post
  12. Concatination problem in port map in vhdl

    Started by moonshine8995, 28th October 2017 07:24
    • Replies: 3
    • Views: 576
    1st November 2017, 15:38 Go to last post
  13. [SOLVED] VHDL - Illegal choice in record aggregate.

    Started by wesleytaylor, 30th October 2017 14:02
    • Replies: 5
    • Views: 568
    1st November 2017, 15:37 Go to last post
  14. FX3 Watermark calculation

    Started by player80, 1st November 2017 11:50
    • Replies: 0
    • Views: 432
    1st November 2017, 11:50 Go to last post
    • Replies: 0
    • Views: 313
    1st November 2017, 11:49 Go to last post
  15. Pin to Clock routing warning after implementation

    Started by msdarvishi, 27th October 2017 23:48
    • Replies: 18
    • Views: 1,183
    31st October 2017, 17:04 Go to last post