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Threads 31 to 60 of 21886

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] Altering some bits of a RAM location

    Started by rafimiet, 6th October 2017 06:53
    • Replies: 2
    • Views: 315
    6th October 2017, 08:10 Go to last post
  2. [SOLVED] clearing the contents of single port RAM

    Started by rafimiet, 4th October 2017 13:17
    • Replies: 13
    • Views: 534
    6th October 2017, 04:28 Go to last post
  3. [Synth 8-27] complex assignment not supported

    Started by rafimiet, 5th October 2017 10:41
    • Replies: 4
    • Views: 456
    6th October 2017, 04:23 Go to last post
    • Replies: 1
    • Views: 347
    4th October 2017, 14:05 Go to last post
  4. MAX II cpld volatile programming

    Started by hareeshP, 3rd October 2017 13:08
    • Replies: 4
    • Views: 440
    4th October 2017, 06:40 Go to last post
    • Replies: 2
    • Views: 404
    3rd October 2017, 18:31 Go to last post
  5. Running multiple program on flash

    Started by beginner_EDA, 2nd October 2017 13:28
    • Replies: 5
    • Views: 369
    2nd October 2017, 18:25 Go to last post
  6. Cyclone 5 sockit usb_uart port

    Started by dipin, 30th September 2017 10:47
    • Replies: 6
    • Views: 442
    2nd October 2017, 15:53 Go to last post
  7. problem by vivado in Rom Extraction from file !

    Started by Port Map, 2nd October 2017 11:50
    • Replies: 6
    • Views: 274
    2nd October 2017, 15:52 Go to last post
  8. Help in encrypting or obfuscation of a design!

    Started by Port Map, 29th September 2017 13:30
    • Replies: 6
    • Views: 706
    30th September 2017, 15:16 Go to last post
  9. Cyclone IV learning board

    Started by andrew_que, 8th August 2017 16:26
    • Replies: 4
    • Views: 700
    30th September 2017, 14:39 Go to last post
  10. Simple circuit not working.... VHDL

    Started by strange_steve, 29th September 2017 00:26
    • Replies: 8
    • Views: 721
    30th September 2017, 10:50 Go to last post
  11. Morton Scan or Z-Scan in vhdl

    Started by rafimiet, 28th September 2017 05:51
    • Replies: 3
    • Views: 389
    29th September 2017, 08:09 Go to last post
    • Replies: 1
    • Views: 358
    28th September 2017, 15:39 Go to last post
  12. testing a variable-length value

    Started by Binome, 27th September 2017 14:55
    • Replies: 5
    • Views: 497
    28th September 2017, 09:41 Go to last post
  13. synchronisation question

    Started by Binome, 27th September 2017 10:10
    • Replies: 5
    • Views: 398
    28th September 2017, 09:39 Go to last post
  14. I2C delay between SCL and SDA

    Started by manush30, 14th September 2017 15:44
    • Replies: 8
    • Views: 820
    27th September 2017, 10:04 Go to last post
  15. Serial Shift Register Network --> SPI Network and distributed RAM

    Started by mmprestine, 22nd September 2017 17:42
    2 Pages
    1 2
    • Replies: 20
    • Views: 1,221
    26th September 2017, 07:39 Go to last post
    • Replies: 12
    • Views: 1,161
    25th September 2017, 15:51 Go to last post
  16. Design of FPGA and PLDs

    Started by garimella, 21st September 2017 09:26
    • Replies: 7
    • Views: 686
    25th September 2017, 09:41 Go to last post
  17. [ALTERA] how can I manage several QSF files?

    Started by ivlsi, 21st September 2017 15:25
    • Replies: 12
    • Views: 897
    22nd September 2017, 11:40 Go to last post
  18. Logic scope coding approach

    Started by promach, 16th September 2017 10:15
    2 Pages
    1 2
    • Replies: 23
    • Views: 1,431
    21st September 2017, 15:36 Go to last post
  19. Frame buffer controller with dual_clock FIFO

    Started by Taki_comp, 19th September 2017 18:22
    • Replies: 6
    • Views: 539
    20th September 2017, 04:40 Go to last post
    • Replies: 2
    • Views: 414
    19th September 2017, 10:28 Go to last post
  20. Is that considered a combinatorial loop and how bad is it ?

    Started by joul, 16th September 2017 16:01
    • Replies: 8
    • Views: 647
    18th September 2017, 10:16 Go to last post
  21. How to Declare a 3D array as an input inside the port

    Started by Yogeshwaran, 16th September 2017 12:15
    • Replies: 4
    • Views: 478
    17th September 2017, 15:54 Go to last post
  22. Reading ufm of max ii

    Started by hareeshP, 14th September 2017 14:41
    • Replies: 10
    • Views: 662
    17th September 2017, 09:27 Go to last post
    • Replies: 3
    • Views: 524
    16th September 2017, 19:04 Go to last post
  23. need some help to design digital circuit

    Started by Adnan86, 15th September 2017 19:08
    • Replies: 12
    • Views: 718
    16th September 2017, 15:55 Go to last post
    • Replies: 3
    • Views: 551
    15th September 2017, 19:18 Go to last post