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Threads 31 to 60 of 21555

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 1
    • Views: 131
    20th April 2017, 08:29 Go to last post
  1. Difference between FIFO and buffer

    Started by viyaaloth, 20th April 2017 07:11
    • Replies: 1
    • Views: 122
    20th April 2017, 08:21 Go to last post
  2. Xilinx: 7 series FPGA Transreceiver

    Started by vivekvlsi, 19th April 2017 21:20
    • Replies: 3
    • Views: 299
    20th April 2017, 01:34 Go to last post
  3. Suggestion of relay for controlling FPGA

    Started by junly, 18th April 2017 11:17
    • Replies: 3
    • Views: 281
    19th April 2017, 07:54 Go to last post
  4. frequency divider using counter

    Started by viyaaloth, 18th April 2017 10:41
    • Replies: 1
    • Views: 176
    18th April 2017, 11:14 Go to last post
  5. binary multiplication

    Started by emerson_11, 18th April 2017 06:22
    • Replies: 2
    • Views: 220
    18th April 2017, 06:58 Go to last post
    • Replies: 18
    • Views: 727
    18th April 2017, 01:18 Go to last post
  6. spartan6 enable input signal remains latched

    Started by moro, 16th April 2017 18:55
    • Replies: 6
    • Views: 295
    18th April 2017, 00:38 Go to last post
    • Replies: 3
    • Views: 272
    17th April 2017, 18:27 Go to last post
  7. DE2-115 development error

    Started by CaiMing, 17th April 2017 03:20
    • Replies: 1
    • Views: 128
    17th April 2017, 05:27 Go to last post
  8. [SOLVED] VHDL Programming Help

    Started by arve9066, 13th April 2017 23:19
    • Replies: 2
    • Views: 229
    17th April 2017, 01:36 Go to last post
    • Replies: 4
    • Views: 301
    16th April 2017, 01:55 Go to last post
  9. [SOLVED] Verilog Programming problem

    Started by jai5605, 14th April 2017 19:23
    • Replies: 2
    • Views: 265
    15th April 2017, 14:48 Go to last post
    • Replies: 14
    • Views: 491
    15th April 2017, 14:13 Go to last post
    • Replies: 0
    • Views: 132
    15th April 2017, 05:35 Go to last post
  10. 4byte data is not flowing between two modules in verilog

    Started by moro, 13th April 2017 20:06
    • Replies: 1
    • Views: 222
    13th April 2017, 23:34 Go to last post
  11. Altera Cyclone II mini

    Started by mahmood.n, 12th April 2017 15:12
    • Replies: 14
    • Views: 481
    13th April 2017, 19:55 Go to last post
  12. parallel interface for data transferring

    Started by viyaaloth, 12th April 2017 09:05
    • Replies: 5
    • Views: 390
    13th April 2017, 14:35 Go to last post
    • Replies: 5
    • Views: 205
    13th April 2017, 13:39 Go to last post
    • Replies: 6
    • Views: 257
    13th April 2017, 12:38 Go to last post
    • Replies: 6
    • Views: 343
    13th April 2017, 09:53 Go to last post
  13. VHDL one clock pulse in 0.5sec

    Started by hardware_guy, 12th April 2017 23:26
    • Replies: 4
    • Views: 243
    13th April 2017, 03:43 Go to last post
  14. Standard interface for DAQ IP

    Started by viyaaloth, 4th April 2017 12:08
    • Replies: 18
    • Views: 697
    12th April 2017, 15:48 Go to last post
  15. Moved: Synchronization logic for DAQ

    Started by viyaaloth, 12th April 2017 17:36
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    • Replies: 3
    • Views: 324
    12th April 2017, 08:55 Go to last post
  16. arithmetic addition for binary digits

    Started by ashok12, 11th April 2017 07:56
    • Replies: 11
    • Views: 360
    12th April 2017, 08:28 Go to last post
    • Replies: 5
    • Views: 298
    12th April 2017, 00:24 Go to last post
  17. Moved: Generic interface for DAQ IP

    Started by viyaaloth, 11th April 2017 16:48
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  18. Multiplier from IPcore

    Started by emerson_11, 11th April 2017 07:47
    • Replies: 3
    • Views: 247
    11th April 2017, 16:23 Go to last post
  19. Time stamps to each data samples

    Started by viyaaloth, 11th April 2017 09:25
    • Replies: 4
    • Views: 269
    11th April 2017, 16:17 Go to last post