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Threads 31 to 60 of 21882

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. MAX II cpld volatile programming

    Started by hareeshP, 3rd October 2017 13:08
    • Replies: 4
    • Views: 437
    4th October 2017, 06:40 Go to last post
    • Replies: 2
    • Views: 403
    3rd October 2017, 18:31 Go to last post
  2. Running multiple program on flash

    Started by beginner_EDA, 2nd October 2017 13:28
    • Replies: 5
    • Views: 364
    2nd October 2017, 18:25 Go to last post
  3. Cyclone 5 sockit usb_uart port

    Started by dipin, 30th September 2017 10:47
    • Replies: 6
    • Views: 435
    2nd October 2017, 15:53 Go to last post
  4. problem by vivado in Rom Extraction from file !

    Started by Port Map, 2nd October 2017 11:50
    • Replies: 6
    • Views: 271
    2nd October 2017, 15:52 Go to last post
  5. Help in encrypting or obfuscation of a design!

    Started by Port Map, 29th September 2017 13:30
    • Replies: 6
    • Views: 703
    30th September 2017, 15:16 Go to last post
  6. Cyclone IV learning board

    Started by andrew_que, 8th August 2017 16:26
    • Replies: 4
    • Views: 696
    30th September 2017, 14:39 Go to last post
  7. Simple circuit not working.... VHDL

    Started by strange_steve, 29th September 2017 00:26
    • Replies: 8
    • Views: 710
    30th September 2017, 10:50 Go to last post
  8. Morton Scan or Z-Scan in vhdl

    Started by rafimiet, 28th September 2017 05:51
    • Replies: 3
    • Views: 386
    29th September 2017, 08:09 Go to last post
    • Replies: 1
    • Views: 357
    28th September 2017, 15:39 Go to last post
  9. testing a variable-length value

    Started by Binome, 27th September 2017 14:55
    • Replies: 5
    • Views: 490
    28th September 2017, 09:41 Go to last post
  10. synchronisation question

    Started by Binome, 27th September 2017 10:10
    • Replies: 5
    • Views: 394
    28th September 2017, 09:39 Go to last post
  11. I2C delay between SCL and SDA

    Started by manush30, 14th September 2017 15:44
    • Replies: 8
    • Views: 813
    27th September 2017, 10:04 Go to last post
  12. Serial Shift Register Network --> SPI Network and distributed RAM

    Started by mmprestine, 22nd September 2017 17:42
    2 Pages
    1 2
    • Replies: 20
    • Views: 1,203
    26th September 2017, 07:39 Go to last post
    • Replies: 12
    • Views: 1,147
    25th September 2017, 15:51 Go to last post
  13. Design of FPGA and PLDs

    Started by garimella, 21st September 2017 09:26
    • Replies: 7
    • Views: 678
    25th September 2017, 09:41 Go to last post
  14. [ALTERA] how can I manage several QSF files?

    Started by ivlsi, 21st September 2017 15:25
    • Replies: 12
    • Views: 889
    22nd September 2017, 11:40 Go to last post
  15. Logic scope coding approach

    Started by promach, 16th September 2017 10:15
    2 Pages
    1 2
    • Replies: 23
    • Views: 1,418
    21st September 2017, 15:36 Go to last post
  16. Frame buffer controller with dual_clock FIFO

    Started by Taki_comp, 19th September 2017 18:22
    • Replies: 6
    • Views: 532
    20th September 2017, 04:40 Go to last post
    • Replies: 2
    • Views: 412
    19th September 2017, 10:28 Go to last post
  17. Is that considered a combinatorial loop and how bad is it ?

    Started by joul, 16th September 2017 16:01
    • Replies: 8
    • Views: 646
    18th September 2017, 10:16 Go to last post
  18. How to Declare a 3D array as an input inside the port

    Started by Yogeshwaran, 16th September 2017 12:15
    • Replies: 4
    • Views: 477
    17th September 2017, 15:54 Go to last post
  19. Reading ufm of max ii

    Started by hareeshP, 14th September 2017 14:41
    • Replies: 10
    • Views: 660
    17th September 2017, 09:27 Go to last post
    • Replies: 3
    • Views: 522
    16th September 2017, 19:04 Go to last post
  20. need some help to design digital circuit

    Started by Adnan86, 15th September 2017 19:08
    • Replies: 12
    • Views: 715
    16th September 2017, 15:55 Go to last post
    • Replies: 3
    • Views: 551
    15th September 2017, 19:18 Go to last post
  21. Timestamp implementation in FPGA

    Started by beginner_EDA, 15th September 2017 11:13
    • Replies: 2
    • Views: 446
    15th September 2017, 14:26 Go to last post
  22. Monitoring different clock domains in chipscope pro

    Started by Taki_comp, 14th September 2017 13:22
    • Replies: 3
    • Views: 421
    14th September 2017, 19:35 Go to last post
  23. Timing simulations in vivado

    Started by rafimiet, 14th September 2017 13:58
    • Replies: 4
    • Views: 375
    14th September 2017, 17:56 Go to last post
  24. [SOLVED] "ERROR: [Common 17-165] Too many positional options when parsing

    Started by rafimiet, 13th September 2017 07:55
    • Replies: 7
    • Views: 584
    14th September 2017, 10:51 Go to last post