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Threads 31 to 60 of 22100

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Moved: Altera's Video and Image Processing Suite Demo on the NEEK

    Started by Greedy_Altera, 1st February 2018 10:45
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  2. Latch over flip flop

    Started by shweta.bphc, 31st January 2018 18:12
    • Replies: 4
    • Views: 379
    1st February 2018, 03:05 Go to last post
  3. Standard Path Delays vs. Critical Path Delays

    Started by msdarvishi, 1st February 2018 02:02
    • Replies: 1
    • Views: 284
    1st February 2018, 03:00 Go to last post
  4. Spartan 6 and flash memory data transferring

    Started by JAVADHABIBI, 28th January 2018 14:52
    • Replies: 9
    • Views: 494
    31st January 2018, 14:20 Go to last post
  5. process sensitivity list problem in FSM (VHDL)

    Started by EceWoman, 27th January 2018 21:44
    • Replies: 7
    • Views: 552
    31st January 2018, 13:27 Go to last post
  6. [SOLVED] Gated reset for register

    Started by mjuneja, 29th January 2018 07:44
    • Replies: 8
    • Views: 511
    31st January 2018, 13:17 Go to last post
  7. ISE Does not Recognize Defined Signal

    Started by RosesAreRed, 30th January 2018 21:22
    • Replies: 6
    • Views: 374
    31st January 2018, 12:05 Go to last post
  8. Problem with timing, Back annotation and FPGA chip

    Started by ibrahima, 31st January 2018 02:18
    • Replies: 2
    • Views: 348
    31st January 2018, 08:26 Go to last post
  9. Stucked at UART formal verification

    Started by promach, 29th January 2018 01:29
    • Replies: 8
    • Views: 466
    30th January 2018, 11:29 Go to last post
  10. Need help with implementing a FIR filter using vhdl

    Started by hamid123, 23rd January 2018 14:17
    • Replies: 7
    • Views: 594
    27th January 2018, 21:28 Go to last post
    • Replies: 5
    • Views: 506
    27th January 2018, 07:46 Go to last post
  11. Problem with using components in vhdl

    Started by mhmmdrz92, 25th January 2018 17:59
    • Replies: 5
    • Views: 384
    26th January 2018, 16:02 Go to last post
  12. [SOLVED] reset array of record

    Started by nsgil85, 25th January 2018 07:06
    • Replies: 2
    • Views: 374
    25th January 2018, 09:18 Go to last post
  13. [old software] XC3000/A Software

    Started by DeepTHought, 20th January 2018 16:45
    • Replies: 4
    • Views: 532
    25th January 2018, 01:22 Go to last post
    • Replies: 3
    • Views: 420
    24th January 2018, 08:33 Go to last post
  14. I/O pin FPGA voltage level translation for interfacing

    Started by fpga93, 19th January 2018 09:35
    • Replies: 7
    • Views: 649
    23rd January 2018, 21:36 Go to last post
  15. [SOLVED] [Verilog] Clock enable causes glitch on ouptut - Best resolution

    Started by pigtwo, 20th January 2018 23:07
    • Replies: 5
    • Views: 586
    22nd January 2018, 17:40 Go to last post
    • Replies: 2
    • Views: 370
    22nd January 2018, 17:04 Go to last post
  16. MAX 10 pin assignment error

    Started by hareeshP, 22nd January 2018 13:00
    • Replies: 0
    • Views: 260
    22nd January 2018, 13:00 Go to last post
    • Replies: 0
    • Views: 268
    20th January 2018, 22:43 Go to last post
  17. CY7C68013A labview interface

    Started by jackobian, 12th January 2018 11:04
    • Replies: 1
    • Views: 420
    20th January 2018, 16:55 Go to last post
  18. non responsive vhdl code in FPGA board

    Started by ananthan95, 29th December 2017 06:58
    • Replies: 10
    • Views: 912
    19th January 2018, 09:13 Go to last post
  19. [SOLVED] Integer convert to std_logic_vector ?

    Started by abimann, 30th December 2017 17:33
    • Replies: 3
    • Views: 591
    19th January 2018, 08:48 Go to last post
  20. Error in verilog code for stopwatch

    Started by Nyom, 18th January 2018 22:59
    • Replies: 6
    • Views: 417
    19th January 2018, 01:30 Go to last post
    • Replies: 5
    • Views: 550
    18th January 2018, 14:19 Go to last post
    • Replies: 4
    • Views: 544
    18th January 2018, 10:52 Go to last post
  21. TIBPAL22vp10 compiler

    Started by wjr1955, 17th January 2018 21:28
    • Replies: 1
    • Views: 286
    18th January 2018, 10:05 Go to last post
  22. [SOLVED] How to receive PWM and edit it ?

    Started by abimann, 30th December 2017 17:39
    • Replies: 13
    • Views: 1,141
    16th January 2018, 08:08 Go to last post
  23. Conversion from std_logic_vector to sfixed

    Started by Hugo17, 15th January 2018 08:31
    • Replies: 2
    • Views: 315
    16th January 2018, 07:06 Go to last post
  24. Wait on clocking block input signals

    Started by amvrao, 12th January 2018 12:48
    • Replies: 2
    • Views: 464
    15th January 2018, 15:59 Go to last post