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Threads 31 to 60 of 22201

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Need logic that implement in Verilog coding

    Started by tayyab786, 6th April 2018 08:32
    • Replies: 0
    • Views: 228
    6th April 2018, 08:32 Go to last post
  2. declaring a constant value for all modules in verilog

    Started by dipin, 6th April 2018 06:12
    • Replies: 3
    • Views: 261
    6th April 2018, 07:39 Go to last post
  3. Usage of HP and HR IO banks and their selection

    Started by Alauddin123, 5th April 2018 06:54
    • Replies: 1
    • Views: 319
    5th April 2018, 07:29 Go to last post
  4. 12 Hour Clock using VHDL

    Started by triplel06, 3rd April 2018 01:12
    • Replies: 8
    • Views: 629
    4th April 2018, 16:59 Go to last post
  5. [MOVED] Need Verilog code for Ethernet protocol

    Started by mhafdhia, 4th April 2018 01:30
    • Replies: 2
    • Views: 385
    4th April 2018, 08:52 Go to last post
  6. Interfacing a buzzer with CPLD

    Started by garvind25, 25th March 2018 16:56
    • Replies: 9
    • Views: 683
    3rd April 2018, 18:45 Go to last post
  7. Concurrent constructs in Verilog?

    Started by samg, 2nd April 2018 10:56
    • Replies: 2
    • Views: 304
    3rd April 2018, 10:18 Go to last post
  8. copying a file from fpga to pc without modem

    Started by dipin, 30th March 2018 15:45
    • Replies: 2
    • Views: 369
    1st April 2018, 22:43 Go to last post
  9. Converting an array of std_logic to string

    Started by shaiko, 30th March 2018 11:45
    • Replies: 9
    • Views: 628
    30th March 2018, 23:16 Go to last post
  10. AXI4 stream bus and arbitration

    Started by filip.amator, 30th March 2018 22:47
    • Replies: 0
    • Views: 293
    30th March 2018, 22:47 Go to last post
  11. Queries on JTAG interface for a CPLD based system

    Started by garvind25, 10th March 2018 18:31
    • Replies: 7
    • Views: 670
    29th March 2018, 11:36 Go to last post
  12. Moved: array in if condition in C program

    Started by vilfred, 29th March 2018 09:56
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    • Replies: 10
    • Views: 842
    28th March 2018, 14:02 Go to last post
  13. Overflow pointer cell

    Started by nsgil85, 27th March 2018 17:09
    • Replies: 3
    • Views: 334
    28th March 2018, 11:17 Go to last post
    • Replies: 3
    • Views: 343
    26th March 2018, 15:58 Go to last post
  14. ADC on DEO nano board

    Started by Chinmaye, 22nd March 2018 17:54
    • Replies: 4
    • Views: 474
    25th March 2018, 09:02 Go to last post
    • Replies: 1
    • Views: 352
    24th March 2018, 23:11 Go to last post
  15. Write leveling for single dram DDR3 device

    Started by Alosevskoy, 24th March 2018 12:36
    • Replies: 0
    • Views: 250
    24th March 2018, 12:36 Go to last post
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    • Replies: 2
    • Views: 407
    22nd March 2018, 01:47 Go to last post
  16. How to "ARCTAN" Function in VHDL

    Started by Krishna_k, 13th March 2018 10:33
    • Replies: 7
    • Views: 753
    21st March 2018, 19:32 Go to last post
  17. What is the best method for finding adjacency?

    Started by jalal.baba, 20th March 2018 21:24
    • Replies: 0
    • Views: 350
    20th March 2018, 21:24 Go to last post
    • Replies: 5
    • Views: 472
    20th March 2018, 05:44 Go to last post
  18. [moved] ADC in DEO_NANO board

    Started by Chinmaye, 19th March 2018 18:41
    • Replies: 2
    • Views: 346
    19th March 2018, 20:50 Go to last post
    • Replies: 5
    • Views: 543
    19th March 2018, 12:28 Go to last post
  19. Work window is Altera Quartus II software

    Started by vedika, 15th March 2018 05:19
    • Replies: 2
    • Views: 447
    19th March 2018, 10:21 Go to last post