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Threads 31 to 60 of 21840

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] how to locate the addresses of 1's in std_logic_vector

    Started by rafimiet, 9th September 2017 05:19
    • Replies: 12
    • Views: 421
    10th September 2017, 19:33 Go to last post
  2. [SOLVED] Difference between combinational path delay and minimum period

    Started by rafimiet, 10th September 2017 06:56
    • Replies: 3
    • Views: 270
    10th September 2017, 14:31 Go to last post
  3. FMC Daughter card info

    Started by sreedharvictor, 10th September 2017 11:17
    • Replies: 1
    • Views: 190
    10th September 2017, 11:35 Go to last post
  4. [SOLVED] radix 4 booth multiplier using 3:2 CSA

    Started by virat_gupta, 9th September 2017 10:03
    • Replies: 0
    • Views: 150
    9th September 2017, 10:03 Go to last post
  5. Moved: creating and deleting error due to clock

    Started by ashok12, 9th September 2017 12:04
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  6. verilog code for creating and deleting of clock error.

    Started by ashok12, 8th September 2017 11:20
    • Replies: 5
    • Views: 267
    9th September 2017, 07:18 Go to last post
    • Replies: 0
    • Views: 175
    8th September 2017, 22:42 Go to last post
  7. Shift register will parallel load

    Started by sandy2811, 5th September 2017 13:17
    • Replies: 3
    • Views: 343
    8th September 2017, 15:26 Go to last post
  8. convert Floating point to fix point

    Started by linam, 7th September 2017 10:06
    • Replies: 6
    • Views: 330
    8th September 2017, 11:49 Go to last post
    • Replies: 1
    • Views: 155
    7th September 2017, 16:43 Go to last post
  9. very strange typecast (VHDL)

    Started by LatticeSemiconductor, 28th August 2017 10:57
    • Replies: 5
    • Views: 389
    7th September 2017, 13:13 Go to last post
  10. Counter Preload by any given values

    Started by sandy2811, 1st September 2017 07:55
    • Replies: 12
    • Views: 724
    7th September 2017, 06:12 Go to last post
  11. Strange behaviour of Standard dual-clock FIFO

    Started by Taki_comp, 3rd September 2017 14:19
    • Replies: 10
    • Views: 377
    4th September 2017, 08:18 Go to last post
  12. problem with VHDL mealy sequence detector

    Started by Armand86, 1st September 2017 21:47
    • Replies: 7
    • Views: 368
    2nd September 2017, 19:33 Go to last post
  13. How to design self checking testbench...

    Started by sandy2811, 22nd August 2017 13:10
    • Replies: 3
    • Views: 486
    2nd September 2017, 04:33 Go to last post
  14. Measuring the execution time on FPGA

    Started by doost4, 26th August 2017 18:39
    2 Pages
    1 2
    • Replies: 23
    • Views: 926
    30th August 2017, 16:12 Go to last post
  15. Programmable Priority Encoder

    Started by RatedR, 13th July 2017 17:00
    • Replies: 11
    • Views: 1,512
    29th August 2017, 15:41 Go to last post
  16. Moved: Programmable Priority Encoder

    Started by RatedR, 29th August 2017 15:55
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  17. High level(P4) FPGA programming

    Started by beginner_EDA, 28th August 2017 23:43
    • Replies: 3
    • Views: 384
    29th August 2017, 10:07 Go to last post
    • Replies: 3
    • Views: 369
    28th August 2017, 09:35 Go to last post
    • Replies: 1
    • Views: 346
    27th August 2017, 23:19 Go to last post
  18. Critical path of combinational circuit

    Started by mahmood.n, 30th March 2017 13:11
    • Replies: 12
    • Views: 978
    26th August 2017, 23:10 Go to last post
  19. [SOLVED] Displaying grayscale video feed on HDMI

    Started by Taki_comp, 23rd August 2017 10:57
    • Replies: 2
    • Views: 381
    26th August 2017, 19:54 Go to last post
  20. [SOLVED] ORing even & odd bits of a vector

    Started by rahdirs, 26th August 2017 00:11
    • Replies: 1
    • Views: 369
    26th August 2017, 03:39 Go to last post
  21. Optical extention of a parallel bus

    Started by shaiko, 24th August 2017 15:14
    • Replies: 9
    • Views: 636
    25th August 2017, 18:03 Go to last post
  22. Hotswap in Vhdl using fpga

    Started by hareeshP, 21st August 2017 10:38
    • Replies: 6
    • Views: 436
    25th August 2017, 09:27 Go to last post
  23. [SOLVED] Processes and concurrent signal assignments

    Started by dzafar, 24th August 2017 00:57
    • Replies: 2
    • Views: 420
    25th August 2017, 08:25 Go to last post
  24. Use two separate codes in FPGA

    Started by NJ176, 21st August 2017 10:47
    • Replies: 7
    • Views: 732
    24th August 2017, 03:32 Go to last post