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Threads 31 to 60 of 21963

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 3
    • Views: 558
    8th November 2017, 18:49 Go to last post
    • Replies: 2
    • Views: 359
    8th November 2017, 13:03 Go to last post
    • Replies: 14
    • Views: 1,749
    8th November 2017, 02:58 Go to last post
    • Replies: 3
    • Views: 429
    7th November 2017, 18:30 Go to last post
  1. LCD code for fpga virtex 6

    Started by moonshine8995, 6th November 2017 12:39
    • Replies: 3
    • Views: 634
    7th November 2017, 13:08 Go to last post
  2. Verilog basic coding/naming conventions

    Started by pigtwo, 4th November 2017 21:53
    • Replies: 7
    • Views: 824
    6th November 2017, 04:44 Go to last post
  3. [SOLVED] Latches create in verilog code

    Started by tayyab786, 3rd November 2017 06:03
    • Replies: 6
    • Views: 958
    5th November 2017, 16:47 Go to last post
  4. inout port in an inner component

    Started by rafimiet, 4th November 2017 06:07
    • Replies: 9
    • Views: 802
    5th November 2017, 00:32 Go to last post
  5. Moved: Latches create in verilog code

    Started by tayyab786, 5th November 2017 00:02
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    • Replies: 4
    • Views: 451
    3rd November 2017, 17:34 Go to last post
  6. Active HDL vs Models performance

    Started by shaiko, 3rd November 2017 15:45
    • Replies: 1
    • Views: 362
    3rd November 2017, 16:22 Go to last post
  7. Modelsim console configuration

    Started by wesleytaylor, 2nd November 2017 18:16
    • Replies: 0
    • Views: 557
    2nd November 2017, 18:16 Go to last post
  8. [SOLVED] VHDL - Unknown identify

    Started by wesleytaylor, 30th October 2017 12:13
    • Replies: 4
    • Views: 541
    2nd November 2017, 00:08 Go to last post
    • Replies: 3
    • Views: 654
    1st November 2017, 19:08 Go to last post
  9. Concatination problem in port map in vhdl

    Started by moonshine8995, 28th October 2017 07:24
    • Replies: 3
    • Views: 535
    1st November 2017, 15:38 Go to last post
  10. [SOLVED] VHDL - Illegal choice in record aggregate.

    Started by wesleytaylor, 30th October 2017 14:02
    • Replies: 5
    • Views: 531
    1st November 2017, 15:37 Go to last post
  11. FX3 Watermark calculation

    Started by player80, 1st November 2017 11:50
    • Replies: 0
    • Views: 405
    1st November 2017, 11:50 Go to last post
    • Replies: 0
    • Views: 281
    1st November 2017, 11:49 Go to last post
  12. Pin to Clock routing warning after implementation

    Started by msdarvishi, 27th October 2017 23:48
    • Replies: 18
    • Views: 1,094
    31st October 2017, 17:04 Go to last post
  13. Read and write from test vector file using vhdl

    Started by shiva17, 31st October 2017 10:53
    • Replies: 3
    • Views: 390
    31st October 2017, 12:37 Go to last post
  14. USB programming of Xilinx CPLDs

    Started by garvind25, 20th October 2017 08:00
    • Replies: 8
    • Views: 881
    31st October 2017, 01:20 Go to last post
  15. [SOLVED] VHDL what is possible. Can I have a package within a package

    Started by wesleytaylor, 23rd October 2017 17:08
    • Replies: 9
    • Views: 806
    30th October 2017, 18:26 Go to last post
    • Replies: 1
    • Views: 353
    30th October 2017, 16:37 Go to last post
  16. Packet over 10Gig ethernet Interface

    Started by beginner_EDA, 30th October 2017 14:00
    • Replies: 0
    • Views: 233
    30th October 2017, 14:00 Go to last post
    • Replies: 2
    • Views: 594
    30th October 2017, 10:53 Go to last post
  17. VHDL procedure that simulate the lock function a PLL

    Started by shaiko, 27th October 2017 18:22
    • Replies: 12
    • Views: 1,111
    29th October 2017, 23:37 Go to last post
  18. kcounter loop filter

    Started by manishpatkar, 29th October 2017 12:30
    • Replies: 8
    • Views: 523
    29th October 2017, 17:26 Go to last post
  19. Nested clock in vhdl

    Started by ananthan95, 19th October 2017 12:58
    • Replies: 17
    • Views: 1,027
    29th October 2017, 14:05 Go to last post
    • Replies: 1
    • Views: 291
    27th October 2017, 16:15 Go to last post