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Threads 31 to 60 of 21778

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. jtag uart speed problem

    Started by dipin, 1st August 2017 12:25
    • Replies: 1
    • Views: 554
    1st August 2017, 16:43 Go to last post
  2. FPGA interfacing ADC with sampling rate >150 Msps

    Started by sherif123, 31st July 2017 08:53
    • Replies: 4
    • Views: 456
    31st July 2017, 15:47 Go to last post
  3. [SOLVED] VHDL Equivalent of Verilog Code

    Started by hareeshP, 31st July 2017 12:44
    • Replies: 1
    • Views: 363
    31st July 2017, 13:59 Go to last post
  4. Need help for write code for recurrent block

    Started by Adnan86, 27th July 2017 21:24
    • Replies: 10
    • Views: 1,062
    30th July 2017, 17:15 Go to last post
    • Replies: 3
    • Views: 576
    29th July 2017, 17:32 Go to last post
    • Replies: 19
    • Views: 1,430
    29th July 2017, 08:52 Go to last post
  5. Basic theory needed to learn FPGA

    Started by FootTea, 28th July 2017 08:52
    • Replies: 4
    • Views: 555
    29th July 2017, 00:47 Go to last post
    • Replies: 6
    • Views: 844
    28th July 2017, 07:24 Go to last post
  6. how to use generate&for to do "x = x + a(i)"

    Started by bravoegg, 26th July 2017 15:58
    • Replies: 10
    • Views: 621
    27th July 2017, 16:34 Go to last post
  7. LDPC: Bit-flipping decoding [Hard decision]

    Started by AbinayaSivam, 27th July 2017 08:30
    • Replies: 0
    • Views: 401
    27th July 2017, 08:30 Go to last post
  8. [SOLVED] qsys jtag_uart doubt

    Started by dipin, 25th July 2017 07:03
    • Replies: 7
    • Views: 607
    27th July 2017, 06:35 Go to last post
  9. Signal declaration based on a generic + VHDL

    Started by dpaul, 26th July 2017 13:20
    • Replies: 2
    • Views: 355
    26th July 2017, 14:00 Go to last post
    • Replies: 2
    • Views: 328
    26th July 2017, 13:07 Go to last post
    • Replies: 0
    • Views: 264
    26th July 2017, 09:14 Go to last post
  10. Booting time of MAX 10 FPGA

    Started by hareeshP, 25th July 2017 08:10
    • Replies: 1
    • Views: 440
    25th July 2017, 19:09 Go to last post
  11. verilog implementation of a viterbi decoder

    Started by tanish, 24th July 2017 09:18
    • Replies: 2
    • Views: 428
    25th July 2017, 04:35 Go to last post
  12. VHDL equivalent of Verilog code

    Started by hareeshP, 24th July 2017 07:39
    • Replies: 13
    • Views: 593
    24th July 2017, 23:18 Go to last post
  13. [SOLVED] Is there a way to probe LVDS serializer output

    Started by nsgil85, 23rd July 2017 09:53
    • Replies: 6
    • Views: 696
    24th July 2017, 16:26 Go to last post
  14. 74HC595 implementation in VHDL - URGENT

    Started by Sean_Goddard, 22nd July 2017 21:45
    • Replies: 1
    • Views: 381
    23rd July 2017, 05:16 Go to last post
  15. Is this FPGA board suitable for learning purposes ??

    Started by arbj2, 22nd July 2017 10:00
    • Replies: 3
    • Views: 535
    23rd July 2017, 01:55 Go to last post
    • Replies: 4
    • Views: 356
    22nd July 2017, 20:10 Go to last post
  16. DDR2 interfacing Virtex-5 with MIG 3.6

    Started by aminpix, 22nd July 2017 00:13
    • Replies: 2
    • Views: 392
    22nd July 2017, 20:04 Go to last post
  17. Basic questions regarding NIOS

    Started by mahmood.n, 20th July 2017 10:16
    • Replies: 4
    • Views: 421
    22nd July 2017, 07:50 Go to last post
  18. how to use spi interface with custom ip

    Started by abhishek7, 18th July 2017 09:43
    • Replies: 2
    • Views: 406
    21st July 2017, 23:57 Go to last post
  19. need help for verilog code

    Started by Adnan86, 21st July 2017 14:45
    • Replies: 1
    • Views: 267
    21st July 2017, 14:51 Go to last post
  20. [SOLVED] Making GPIO pin of FPGA high.

    Started by hareeshP, 20th July 2017 14:38
    • Replies: 8
    • Views: 631
    21st July 2017, 14:47 Go to last post
    • Replies: 3
    • Views: 365
    19th July 2017, 14:39 Go to last post
  21. VHDL Constant Declaration

    Started by hareeshP, 19th July 2017 05:16
    • Replies: 13
    • Views: 534
    19th July 2017, 14:09 Go to last post
    • Replies: 5
    • Views: 449
    19th July 2017, 05:04 Go to last post