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Threads 31 to 60 of 21685

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. A pseudo-random number generator

    Started by Binome, 13th June 2017 10:25
    • Replies: 4
    • Views: 249
    13th June 2017, 14:15 Go to last post
  2. WARNING:NgdBuild:486 in xilinx

    Started by ecasha, 13th June 2017 04:25
    • Replies: 1
    • Views: 287
    13th June 2017, 08:46 Go to last post
  3. [SOLVED] FPGA: Different behavior after synthesis

    Started by birbal, 12th June 2017 22:23
    • Replies: 4
    • Views: 408
    12th June 2017, 23:42 Go to last post
  4. Route 455: CLK Net may have excessive skew

    Started by sonika111, 12th June 2017 15:58
    • Replies: 1
    • Views: 269
    12th June 2017, 17:53 Go to last post
  5. I2C with Picoblaze processor

    Started by beginner_EDA, 7th June 2017 11:33
    • Replies: 2
    • Views: 526
    12th June 2017, 09:41 Go to last post
    • Replies: 4
    • Views: 554
    12th June 2017, 07:59 Go to last post
  6. Using a component in loop

    Started by mahmood.n, 10th June 2017 10:34
    • Replies: 6
    • Views: 914
    11th June 2017, 14:20 Go to last post
  7. implementing a graph traversal algorithm on FPGA

    Started by doost4, 7th June 2017 10:16
    • Replies: 14
    • Views: 774
    9th June 2017, 15:39 Go to last post
  8. What to do with unused input pins

    Started by wesleytaylor, 7th June 2017 15:46
    • Replies: 3
    • Views: 407
    9th June 2017, 13:24 Go to last post
  9. Variable width data pulse generator

    Started by bit_an, 8th June 2017 23:09
    • Replies: 2
    • Views: 418
    9th June 2017, 00:33 Go to last post
    • Replies: 1
    • Views: 237
    8th June 2017, 17:22 Go to last post
    • Replies: 13
    • Views: 911
    7th June 2017, 12:22 Go to last post
  10. Fundamentals in Verilog

    Started by bit_an, 6th June 2017 18:05
    • Replies: 1
    • Views: 453
    6th June 2017, 18:31 Go to last post
  11. [moved] Slice count on FPGA ?

    Started by Tarunfpga1, 6th June 2017 17:20
    • Replies: 1
    • Views: 250
    6th June 2017, 17:47 Go to last post
    • Replies: 1
    • Views: 282
    6th June 2017, 16:52 Go to last post
  12. How to know the delay of Mult_add ?

    Started by happsky, 30th May 2017 08:21
    • Replies: 3
    • Views: 500
    6th June 2017, 07:40 Go to last post
    • Replies: 5
    • Views: 532
    5th June 2017, 16:55 Go to last post
    • Replies: 3
    • Views: 495
    5th June 2017, 07:22 Go to last post
  13. cypress usb not detected

    Started by Bosechandran, 27th December 2016 06:38
    • Replies: 2
    • Views: 831
    3rd June 2017, 17:02 Go to last post
    • Replies: 17
    • Views: 1,304
    3rd June 2017, 16:09 Go to last post
  14. [SOLVED] FPGA or CPLD with hadware serial number?

    Started by hardware_guy, 21st May 2017 15:36
    • Replies: 5
    • Views: 616
    3rd June 2017, 11:59 Go to last post
    • Replies: 5
    • Views: 581
    2nd June 2017, 10:29 Go to last post
  15. BRAM is physical memory or virtual memory

    Started by viyaaloth, 1st June 2017 12:18
    • Replies: 1
    • Views: 253
    1st June 2017, 13:56 Go to last post
  16. Timing Constraints for external clocks

    Started by incisive29, 28th May 2017 11:16
    • Replies: 6
    • Views: 549
    31st May 2017, 23:57 Go to last post
  17. Need Help regarding Actel FPGA Area Constraints

    Started by saad_sipra, 10th May 2017 16:06
    • Replies: 19
    • Views: 1,652
    31st May 2017, 23:50 Go to last post
  18. Reduction operator on a multi dimension vector

    Started by rahdirs, 31st May 2017 21:50
    • Replies: 1
    • Views: 260
    31st May 2017, 22:02 Go to last post