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Threads 31 to 60 of 21957

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] Latches create in verilog code

    Started by tayyab786, 3rd November 2017 06:03
    • Replies: 6
    • Views: 935
    5th November 2017, 16:47 Go to last post
  2. inout port in an inner component

    Started by rafimiet, 4th November 2017 06:07
    • Replies: 9
    • Views: 764
    5th November 2017, 00:32 Go to last post
  3. Moved: Latches create in verilog code

    Started by tayyab786, 5th November 2017 00:02
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    •  
    • Replies: 4
    • Views: 418
    3rd November 2017, 17:34 Go to last post
  4. Active HDL vs Models performance

    Started by shaiko, 3rd November 2017 15:45
    • Replies: 1
    • Views: 349
    3rd November 2017, 16:22 Go to last post
  5. Modelsim console configuration

    Started by wesleytaylor, 2nd November 2017 18:16
    • Replies: 0
    • Views: 547
    2nd November 2017, 18:16 Go to last post
  6. [SOLVED] VHDL - Unknown identify

    Started by wesleytaylor, 30th October 2017 12:13
    • Replies: 4
    • Views: 522
    2nd November 2017, 00:08 Go to last post
    • Replies: 3
    • Views: 648
    1st November 2017, 19:08 Go to last post
  7. Concatination problem in port map in vhdl

    Started by moonshine8995, 28th October 2017 07:24
    • Replies: 3
    • Views: 523
    1st November 2017, 15:38 Go to last post
  8. [SOLVED] VHDL - Illegal choice in record aggregate.

    Started by wesleytaylor, 30th October 2017 14:02
    • Replies: 5
    • Views: 505
    1st November 2017, 15:37 Go to last post
  9. FX3 Watermark calculation

    Started by player80, 1st November 2017 11:50
    • Replies: 0
    • Views: 396
    1st November 2017, 11:50 Go to last post
    • Replies: 0
    • Views: 269
    1st November 2017, 11:49 Go to last post
  10. Pin to Clock routing warning after implementation

    Started by msdarvishi, 27th October 2017 23:48
    • Replies: 18
    • Views: 1,033
    31st October 2017, 17:04 Go to last post
  11. Read and write from test vector file using vhdl

    Started by shiva17, 31st October 2017 10:53
    • Replies: 3
    • Views: 377
    31st October 2017, 12:37 Go to last post
  12. USB programming of Xilinx CPLDs

    Started by garvind25, 20th October 2017 08:00
    • Replies: 8
    • Views: 870
    31st October 2017, 01:20 Go to last post
  13. [SOLVED] VHDL what is possible. Can I have a package within a package

    Started by wesleytaylor, 23rd October 2017 17:08
    • Replies: 9
    • Views: 778
    30th October 2017, 18:26 Go to last post
    • Replies: 1
    • Views: 344
    30th October 2017, 16:37 Go to last post
  14. Packet over 10Gig ethernet Interface

    Started by beginner_EDA, 30th October 2017 14:00
    • Replies: 0
    • Views: 227
    30th October 2017, 14:00 Go to last post
    • Replies: 2
    • Views: 582
    30th October 2017, 10:53 Go to last post
  15. VHDL procedure that simulate the lock function a PLL

    Started by shaiko, 27th October 2017 18:22
    • Replies: 12
    • Views: 1,077
    29th October 2017, 23:37 Go to last post
  16. kcounter loop filter

    Started by manishpatkar, 29th October 2017 12:30
    • Replies: 8
    • Views: 489
    29th October 2017, 17:26 Go to last post
  17. Nested clock in vhdl

    Started by ananthan95, 19th October 2017 12:58
    • Replies: 17
    • Views: 997
    29th October 2017, 14:05 Go to last post
    • Replies: 1
    • Views: 288
    27th October 2017, 16:15 Go to last post
  18. Multiplexer in VHDL with a 2D array and for loop

    Started by moonshine8995, 27th October 2017 12:37
    • Replies: 3
    • Views: 296
    27th October 2017, 15:19 Go to last post
  19. 10 Gig ethernet Packet capture tool

    Started by beginner_EDA, 27th October 2017 12:03
    • Replies: 1
    • Views: 257
    27th October 2017, 12:48 Go to last post
  20. Convert std_logic_vector to integer

    Started by moonshine8995, 26th October 2017 13:05
    • Replies: 7
    • Views: 380
    27th October 2017, 12:11 Go to last post
  21. Problem to understand internal architecture of JTAG

    Started by sandy2811, 25th October 2017 05:43
    • Replies: 7
    • Views: 723
    27th October 2017, 11:02 Go to last post
  22. Function 'test' could not be resolved in HLS

    Started by mouhamedmb, 27th October 2017 10:23
    • Replies: 0
    • Views: 195
    27th October 2017, 10:23 Go to last post
  23. [SOLVED] System Verilog error in modelsim with enum types.

    Started by vipinlal, 26th October 2017 15:06
    • Replies: 3
    • Views: 279
    26th October 2017, 16:52 Go to last post