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Threads 31 to 60 of 22012

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. FPGA-Based Christmas project

    Started by bwarlord01, 6th December 2017 19:29
    • Replies: 3
    • Views: 492
    7th December 2017, 02:46 Go to last post
  2. What is Most Economic FPGA?

    Started by Zerox100, 5th December 2017 16:04
    • Replies: 2
    • Views: 432
    6th December 2017, 12:59 Go to last post
    • Replies: 0
    • Views: 281
    6th December 2017, 12:18 Go to last post
  3. Vendor specific macros for Igloo2

    Started by filip.amator, 5th December 2017 23:15
    • Replies: 2
    • Views: 536
    6th December 2017, 11:38 Go to last post
  4. ppg database regarding

    Started by josephine1234, 5th December 2017 12:00
    • Replies: 1
    • Views: 278
    5th December 2017, 12:13 Go to last post
  5. FPGA Ethernet interface

    Started by Vlad., 3rd December 2017 19:11
    • Replies: 3
    • Views: 1,161
    4th December 2017, 09:51 Go to last post
  6. Regarding Verilog codes

    Started by josephine1234, 1st December 2017 06:06
    • Replies: 5
    • Views: 852
    2nd December 2017, 13:07 Go to last post
  7. SPI communication (ALTERA board)

    Started by MiLaNa1995, 30th November 2017 14:19
    • Replies: 1
    • Views: 402
    2nd December 2017, 09:36 Go to last post
  8. Multiple users of a DDR interface

    Started by shaiko, 29th November 2017 21:08
    • Replies: 14
    • Views: 1,162
    2nd December 2017, 09:31 Go to last post
  9. Coding help in Verilog

    Started by josephine1234, 1st December 2017 06:04
    • Replies: 4
    • Views: 482
    1st December 2017, 13:18 Go to last post
  10. Implementation of output wrt clock in verilog

    Started by kapaa, 30th November 2017 08:24
    • Replies: 5
    • Views: 585
    1st December 2017, 07:01 Go to last post
  11. Interfacing a VGA port with a PLD

    Started by garvind25, 25th October 2017 07:16
    • Replies: 10
    • Views: 1,071
    1st December 2017, 06:10 Go to last post
  12. modelsim error during RTL simulation

    Started by hareeshP, 30th November 2017 15:07
    • Replies: 8
    • Views: 529
    30th November 2017, 19:33 Go to last post
  13. Data not appearing in waveform window

    Started by athuluri_mounika, 28th November 2017 13:08
    • Replies: 5
    • Views: 533
    30th November 2017, 19:22 Go to last post
  14. FPGA Vertex -6 ML605

    Started by tayyab786, 29th November 2017 03:04
    • Replies: 4
    • Views: 570
    30th November 2017, 17:06 Go to last post
  15. KCU105 configuration

    Started by wesleytaylor, 30th November 2017 12:14
    • Replies: 0
    • Views: 318
    30th November 2017, 12:14 Go to last post
  16. Programming an fpga board

    Started by moonshine8995, 29th November 2017 14:17
    • Replies: 2
    • Views: 413
    30th November 2017, 11:39 Go to last post
  17. using chipscope to check signals in a design

    Started by moonshine8995, 29th November 2017 09:00
    • Replies: 2
    • Views: 369
    29th November 2017, 19:47 Go to last post
  18. Microsemi FPGA, remove clock buffer

    Started by cocopa, 29th November 2017 12:12
    • Replies: 1
    • Views: 355
    29th November 2017, 19:41 Go to last post
    • Replies: 1
    • Views: 363
    29th November 2017, 17:49 Go to last post
  19. coding help needed in verilog

    Started by josephine1234, 29th November 2017 05:53
    • Replies: 3
    • Views: 360
    29th November 2017, 08:29 Go to last post
  20. BRAM vs LUTRAM resources

    Started by rafimiet, 27th November 2017 07:16
    • Replies: 1
    • Views: 564
    27th November 2017, 07:45 Go to last post
  21. DAQ system with FPGA and 1KHz sampling rate

    Started by Vlad., 25th November 2017 17:16
    • Replies: 14
    • Views: 1,373
    26th November 2017, 13:15 Go to last post
    • Replies: 4
    • Views: 690
    25th November 2017, 20:48 Go to last post
  22. Mapping block RAMs to specific address space

    Started by sajjad.hussain, 23rd November 2017 00:08
    • Replies: 4
    • Views: 1,178
    24th November 2017, 16:49 Go to last post
  23. Asynchronous fifo cdc question

    Started by promach, 21st November 2017 06:51
    • Replies: 1
    • Views: 521
    24th November 2017, 02:00 Go to last post
    • Replies: 0
    • Views: 753
    23rd November 2017, 05:26 Go to last post
  24. Error in verilog code

    Started by josephine1234, 21st November 2017 07:25
    • Replies: 5
    • Views: 796
    22nd November 2017, 22:22 Go to last post
    • Replies: 1
    • Views: 368
    22nd November 2017, 16:34 Go to last post
  25. [SOLVED] IOBUF primative doesn't behave the way i want

    Started by wesleytaylor, 21st November 2017 16:25
    • Replies: 3
    • Views: 857
    22nd November 2017, 14:31 Go to last post