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Threads 331 to 360 of 22099

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: saving the the content of a nios2 console.

    Started by dipin, 17th August 2017 10:06
    • Replies: 0
    • Views: 470
    17th August 2017, 10:06 Go to last post
  2. Closed: how to understand Xilinx CORDIC V6.0 atan input method

    Started by DilshanSampath, 15th August 2017 21:32
    • Replies: 3
    • Views: 747
    16th August 2017, 11:31 Go to last post
  3. [SOLVED]Closed: Writing fresh data to a file after re-launch of sim in Vivado2017.2 + VHDL

    Started by dpaul, 15th August 2017 11:50
    • Replies: 5
    • Views: 539
    15th August 2017, 19:39 Go to last post
  4. Closed: a logic to detect FPGA family?

    Started by Port Map, 13th August 2017 10:42
    • Replies: 8
    • Views: 710
    15th August 2017, 09:31 Go to last post
  5. Closed: synchronize data with general GPIO clk

    Started by nsgil85, 13th August 2017 11:27
    • Replies: 8
    • Views: 706
    14th August 2017, 15:59 Go to last post
    • Replies: 5
    • Views: 852
    12th August 2017, 20:54 Go to last post
    • Replies: 5
    • Views: 609
    12th August 2017, 13:59 Go to last post
  6. Closed: How to snyc one 7 Series Transceiver to anothe

    Started by beginner_EDA, 11th August 2017 13:42
    • Replies: 3
    • Views: 504
    12th August 2017, 09:32 Go to last post
  7. Closed: how to fix WARNING:Xst:1710

    Started by tanish, 12th August 2017 08:07
    • Replies: 1
    • Views: 363
    12th August 2017, 08:42 Go to last post
  8. Closed: optimized CDR settings for 12G-SDI

    Started by beginner_EDA, 10th August 2017 09:58
    • Replies: 1
    • Views: 490
    11th August 2017, 15:56 Go to last post
  9. Closed: VHDL Instantiation in modelSim

    Started by hareeshP, 10th August 2017 06:57
    • Replies: 14
    • Views: 920
    10th August 2017, 19:16 Go to last post
  10. Closed: Cannot Read Data in 1-Port RAM IP Core

    Started by learni, 10th August 2017 09:40
    • Replies: 2
    • Views: 607
    10th August 2017, 18:52 Go to last post
  11. Closed: ADC and DAC interface for Spartan - 3A

    Started by NJ176, 10th August 2017 11:02
    • Replies: 1
    • Views: 350
    10th August 2017, 13:13 Go to last post
  12. Closed: xilinx ip core to calculate square root without cordic

    Started by DilshanSampath, 5th August 2017 16:21
    • Replies: 10
    • Views: 1,227
    9th August 2017, 06:27 Go to last post
  13. Closed: Same constant name in 2 different packages

    Started by shaiko, 5th August 2017 12:53
    • Replies: 11
    • Views: 1,304
    7th August 2017, 10:23 Go to last post
  14. Closed: FPGA timing due to Dist ram

    Started by Alauddin123, 6th August 2017 10:42
    • Replies: 1
    • Views: 517
    6th August 2017, 12:08 Go to last post
  15. Closed: use C to program FPGA

    Started by matin-kh, 2nd July 2017 12:39
    • Replies: 11
    • Views: 2,371
    4th August 2017, 23:04 Go to last post
  16. Closed: substitution for loops in design compiler

    Started by moonshine8995, 4th August 2017 11:04
    • Replies: 4
    • Views: 791
    4th August 2017, 18:02 Go to last post
  17. Closed: Amp ADC interfacing using VHDL for Spartan-3A

    Started by NJ176, 31st July 2017 09:44
    • Replies: 4
    • Views: 982
    4th August 2017, 17:49 Go to last post
  18. [SOLVED]Closed: xilinx timing analyze using modelsim SE

    Started by tanish, 3rd August 2017 17:53
    • Replies: 1
    • Views: 703
    3rd August 2017, 20:53 Go to last post
  19. Closed: Minimal HDMI connection pins , only 8 pins is enough ??

    Started by abimann, 3rd August 2017 11:44
    • Replies: 2
    • Views: 587
    3rd August 2017, 16:31 Go to last post
  20. Closed: Verilog Assignment code

    Started by hareeshP, 1st August 2017 10:23
    • Replies: 4
    • Views: 950
    2nd August 2017, 06:45 Go to last post
  21. Closed: VHDL Register transferring.

    Started by hareeshP, 19th July 2017 13:28
    • Replies: 15
    • Views: 1,275
    2nd August 2017, 06:15 Go to last post
  22. Closed: jtag uart speed problem

    Started by dipin, 1st August 2017 12:25
    • Replies: 1
    • Views: 704
    1st August 2017, 16:43 Go to last post
  23. Closed: FPGA interfacing ADC with sampling rate >150 Msps

    Started by sherif123, 31st July 2017 08:53
    • Replies: 4
    • Views: 770
    31st July 2017, 15:47 Go to last post
  24. [SOLVED]Closed: VHDL Equivalent of Verilog Code

    Started by hareeshP, 31st July 2017 12:44
    • Replies: 1
    • Views: 516
    31st July 2017, 13:59 Go to last post
  25. Closed: Need help for write code for recurrent block

    Started by Adnan86, 27th July 2017 21:24
    • Replies: 10
    • Views: 1,475
    30th July 2017, 17:15 Go to last post
    • Replies: 1
    • Views: 666
    30th July 2017, 04:27 Go to last post
  26. Closed: fpga programmed successfully but it doesn't work correctley

    Started by matin-kh, 26th July 2017 05:14
    • Replies: 3
    • Views: 762
    29th July 2017, 17:32 Go to last post
  27. Closed: how to find area, latency, throughput, power in my design?

    Started by Reeyam, 25th June 2017 01:06
    • Replies: 19
    • Views: 1,949
    29th July 2017, 08:52 Go to last post