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Threads 331 to 360 of 21959

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. BRAM is physical memory or virtual memory

    Started by viyaaloth, 1st June 2017 12:18
    • Replies: 1
    • Views: 336
    1st June 2017, 13:56 Go to last post
  2. Timing Constraints for external clocks

    Started by incisive29, 28th May 2017 11:16
    • Replies: 6
    • Views: 745
    31st May 2017, 23:57 Go to last post
  3. Need Help regarding Actel FPGA Area Constraints

    Started by saad_sipra, 10th May 2017 16:06
    • Replies: 19
    • Views: 2,109
    31st May 2017, 23:50 Go to last post
  4. [SOLVED] Reduction operator on a multi dimension vector

    Started by rahdirs, 31st May 2017 21:50
    • Replies: 1
    • Views: 336
    31st May 2017, 22:02 Go to last post
  5. image rotation with LUTs

    Started by JerryDT, 29th May 2017 21:31
    • Replies: 3
    • Views: 627
    31st May 2017, 11:11 Go to last post
  6. FPGA board for substituting microcontrollers

    Started by Endre, 30th May 2017 15:51
    • Replies: 1
    • Views: 549
    30th May 2017, 21:11 Go to last post
  7. [MOVED]Fetching Pdb file from Actel FPGA

    Started by incisive29, 28th May 2017 10:56
    • Replies: 2
    • Views: 476
    30th May 2017, 17:19 Go to last post
  8. [moved] CLKBUF and INBUF actel FPGA

    Started by incisive29, 28th May 2017 11:01
    • Replies: 2
    • Views: 392
    30th May 2017, 17:17 Go to last post
    • Replies: 1
    • Views: 296
    30th May 2017, 17:13 Go to last post
  9. Reading and Writting to a RAM at the same time

    Started by srpronto, 30th May 2017 14:25
    • Replies: 3
    • Views: 396
    30th May 2017, 16:23 Go to last post
  10. [SOLVED] Crystal Oscillators instead of FPGA Clock

    Started by Kibos, 26th May 2017 13:41
    • Replies: 9
    • Views: 1,391
    30th May 2017, 14:58 Go to last post
    • Replies: 0
    • Views: 290
    28th May 2017, 17:41 Go to last post
  11. Reading a block RAM Xilinx IP Core

    Started by beginner_EDA, 26th May 2017 13:04
    • Replies: 3
    • Views: 563
    26th May 2017, 16:11 Go to last post
    • Replies: 8
    • Views: 1,120
    26th May 2017, 03:47 Go to last post
  12. creating axi slave peripheral in vivado ?

    Started by hcu, 25th May 2017 16:58
    • Replies: 3
    • Views: 525
    25th May 2017, 19:10 Go to last post
  13. Closed: Simulation of hierarchy design does not work !

    Started by msdarvishi, 24th May 2017 02:21
    • Replies: 7
    • Views: 553
    24th May 2017, 16:57 Go to last post
  14. Closed: Declaring multidimensional array problem in Modelsim

    Started by manik045, 20th May 2017 12:46
    • Replies: 10
    • Views: 978
    24th May 2017, 08:38 Go to last post
  15. Closed: SPI sample code using FPGA

    Started by myjoe1026, 22nd May 2017 07:14
    • Replies: 13
    • Views: 941
    24th May 2017, 04:02 Go to last post
    • Replies: 10
    • Views: 1,074
    23rd May 2017, 12:44 Go to last post
    • Replies: 6
    • Views: 610
    23rd May 2017, 06:50 Go to last post
  16. Closed: i2c vhdl example code

    Started by amir_rch, 20th May 2017 13:14
    • Replies: 4
    • Views: 748
    22nd May 2017, 16:12 Go to last post
  17. Closed: B&R Automation Studio

    Started by sunshine2016, 12th May 2017 21:23
    • Replies: 3
    • Views: 591
    22nd May 2017, 16:09 Go to last post
  18. Closed: 128x64zw lcd interfacing with fpga

    Started by zacief, 16th May 2017 12:43
    • Replies: 10
    • Views: 958
    21st May 2017, 13:39 Go to last post
  19. Closed: Unable to infer RAM on Quartus Prime

    Started by FecP, 18th May 2017 17:00
    • Replies: 8
    • Views: 955
    20th May 2017, 09:29 Go to last post
  20. Closed: Working with a SPARTAN6 board

    Started by mahmood.n, 18th May 2017 12:26
    • Replies: 13
    • Views: 865
    20th May 2017, 08:24 Go to last post
  21. [SOLVED]Closed: verilog code for addition of contents in the memory

    Started by ecasha, 17th May 2017 18:35
    • Replies: 8
    • Views: 817
    19th May 2017, 06:46 Go to last post
  22. Closed: RPN Calculator using VHDL

    Started by NightOWL, 18th May 2017 20:30
    • Replies: 1
    • Views: 497
    19th May 2017, 00:23 Go to last post
  23. Closed: VHDL Design Problem Issues

    Started by dzafar, 15th May 2017 10:20
    • Replies: 14
    • Views: 1,010
    17th May 2017, 23:22 Go to last post