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Threads 301 to 330 of 21555

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Using data that read from memory increase fpga resources

    Started by Igal24, 26th December 2016 13:07
    • Replies: 5
    • Views: 340
    27th December 2016, 10:13 Go to last post
    • Replies: 4
    • Views: 364
    27th December 2016, 10:06 Go to last post
  2. verilog delay problem

    Started by Bosechandran, 26th December 2016 10:00
    • Replies: 3
    • Views: 369
    27th December 2016, 07:02 Go to last post
  3. cypress usb not detected

    Started by Bosechandran, 27th December 2016 06:38
    • Replies: 0
    • Views: 265
    27th December 2016, 06:38 Go to last post
  4. supply for fpga board

    Started by Bosechandran, 26th December 2016 08:54
    • Replies: 2
    • Views: 308
    26th December 2016, 09:33 Go to last post
  5. SDC set input delay has no effect

    Started by shaiko, 24th December 2016 17:45
    • Replies: 12
    • Views: 424
    26th December 2016, 08:53 Go to last post
  6. Picoblaze Spartan 3E I2C

    Started by FecP, 6th December 2016 18:21
    • Replies: 6
    • Views: 375
    25th December 2016, 21:56 Go to last post
  7. Question about VCD content

    Started by ruwan2, 25th December 2016 00:56
    • Replies: 1
    • Views: 305
    25th December 2016, 09:01 Go to last post
  8. Hierarchically forcing VHDL signals during simulation

    Started by shaiko, 22nd December 2016 11:04
    • Replies: 7
    • Views: 289
    23rd December 2016, 13:39 Go to last post
    • Replies: 1
    • Views: 315
    22nd December 2016, 14:00 Go to last post
  9. configuration a spartan 3 with FX2LP in C++

    Started by JAVADHABIBI, 9th December 2016 10:59
    • Replies: 14
    • Views: 472
    22nd December 2016, 04:54 Go to last post
  10. Xilinx 7 Series transceiver

    Started by beginner_EDA, 21st December 2016 11:25
    • Replies: 0
    • Views: 233
    21st December 2016, 11:25 Go to last post
  11. [moved] How do I reset my FPGA by using xilinx pll?

    Started by coshy, 15th December 2016 14:46
    • Replies: 9
    • Views: 435
    21st December 2016, 09:13 Go to last post
  12. Want to source part of verilog file in VCS

    Started by sanketphapale45, 19th December 2016 08:03
    • Replies: 1
    • Views: 305
    19th December 2016, 14:04 Go to last post
  13. Peak Power Estimation Using Xilinx 13.2 XPA

    Started by sajjad.hussain, 17th December 2016 14:17
    • Replies: 0
    • Views: 263
    17th December 2016, 14:17 Go to last post
  14. [verilog] How is a always@* block synthesized

    Started by pigtwo, 16th December 2016 22:48
    • Replies: 2
    • Views: 508
    17th December 2016, 00:53 Go to last post
  15. interfacing Artix 7 for image processing algorithm

    Started by rafimiet, 14th December 2016 11:12
    • Replies: 3
    • Views: 319
    16th December 2016, 11:39 Go to last post
    • Replies: 0
    • Views: 300
    15th December 2016, 20:21 Go to last post
  16. Help - Multiple driver message

    Started by manush30, 15th December 2016 14:00
    • Replies: 3
    • Views: 290
    15th December 2016, 17:01 Go to last post
  17. Issue the FIFO implementation

    Started by coshy, 14th December 2016 02:35
    • Replies: 3
    • Views: 343
    14th December 2016, 10:56 Go to last post
  18. variable size vector or array in VHDL

    Started by rafimiet, 13th December 2016 07:44
    • Replies: 2
    • Views: 303
    14th December 2016, 06:28 Go to last post
  19. sequential logic breaks down, possibly glitches?

    Started by bravoegg, 12th December 2016 16:00
    • Replies: 5
    • Views: 294
    13th December 2016, 10:04 Go to last post
  20. Combining 2 digital signals?

    Started by UsernameIsValid, 12th December 2016 22:26
    • Replies: 3
    • Views: 322
    13th December 2016, 02:01 Go to last post
  21. Verilog Elevator Control Code

    Started by KatNms, 11th December 2016 22:16
    • Replies: 4
    • Views: 394
    12th December 2016, 17:27 Go to last post
  22. comparing values of memory locations

    Started by p11, 10th December 2016 19:21
    • Replies: 6
    • Views: 426
    12th December 2016, 17:00 Go to last post
  23. modelsim: change the vsim.wlf location

    Started by ayden23, 11th December 2016 21:05
    • Replies: 1
    • Views: 305
    12th December 2016, 12:48 Go to last post
  24. USB3 communiation between the PC and custom FPGA board

    Started by sherif123, 11th December 2016 14:50
    • Replies: 1
    • Views: 273
    11th December 2016, 19:21 Go to last post
  25. input clock precision loss after DCM

    Started by bravoegg, 8th December 2016 12:47
    • Replies: 4
    • Views: 299
    11th December 2016, 09:24 Go to last post