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Threads 301 to 330 of 21681

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. How to store Nios II program on external SDRAM?

    Started by matrixofdynamism, 28th February 2017 11:54
    • Replies: 1
    • Views: 284
    28th February 2017, 13:34 Go to last post
    • Replies: 1
    • Views: 247
    28th February 2017, 12:55 Go to last post
  2. how to know while loop number of iteration ?

    Started by jojo26, 27th February 2017 13:15
    • Replies: 6
    • Views: 328
    28th February 2017, 09:54 Go to last post
    • Replies: 10
    • Views: 441
    27th February 2017, 23:12 Go to last post
    • Replies: 1
    • Views: 223
    27th February 2017, 20:48 Go to last post
    • Replies: 1
    • Views: 223
    27th February 2017, 18:59 Go to last post
  3. How to do routing using Tcl scripts?

    Started by msdarvishi, 27th February 2017 18:19
    • Replies: 0
    • Views: 212
    27th February 2017, 18:19 Go to last post
  4. how does SPI protocol has higher throughput than I2C?

    Started by kaushikrvs, 23rd February 2017 11:33
    • Replies: 10
    • Views: 361
    26th February 2017, 22:45 Go to last post
  5. weird vhdl simulation result

    Started by muhammad_ali, 25th February 2017 16:07
    • Replies: 4
    • Views: 318
    25th February 2017, 20:10 Go to last post
  6. how to interface ov7670 to altera max 2 cpld

    Started by kalashini, 25th February 2017 04:42
    • Replies: 0
    • Views: 277
    25th February 2017, 04:42 Go to last post
  7. multiplexing an array of sensors using a FPGA

    Started by gpascu, 15th February 2017 20:07
    • Replies: 5
    • Views: 402
    24th February 2017, 23:37 Go to last post
    • Replies: 6
    • Views: 332
    24th February 2017, 15:36 Go to last post
  8. fir filter output verification

    Started by dipin, 10th February 2017 14:38
    • Replies: 12
    • Views: 546
    24th February 2017, 08:09 Go to last post
  9. AXI4 master bus functional model implementation

    Started by tariq786, 23rd February 2017 01:31
    • Replies: 1
    • Views: 269
    23rd February 2017, 15:27 Go to last post
  10. [SOLVED] SPI FPGA Maximum rating

    Started by rayhh27, 23rd February 2017 10:00
    • Replies: 1
    • Views: 266
    23rd February 2017, 14:30 Go to last post
  11. FPGA development board suggestion

    Started by arve9066, 21st February 2017 18:19
    • Replies: 7
    • Views: 315
    23rd February 2017, 13:22 Go to last post
  12. "std_logic_vector" Related Questions

    Started by dzafar, 22nd February 2017 20:52
    • Replies: 1
    • Views: 190
    22nd February 2017, 21:03 Go to last post
  13. Maximum FPGA PWM Resolution

    Started by asdf44, 21st February 2017 19:06
    • Replies: 12
    • Views: 370
    22nd February 2017, 17:57 Go to last post
  14. Vhdl netlist merging

    Started by hanif, 22nd February 2017 11:07
    • Replies: 0
    • Views: 266
    22nd February 2017, 11:07 Go to last post
  15. Is the prefix sum operator synthesizable in verilog??

    Started by kaushikrvs, 22nd February 2017 06:27
    • Replies: 2
    • Views: 197
    22nd February 2017, 07:49 Go to last post
  16. Functions and description of lines

    Started by Binome, 21st February 2017 12:18
    • Replies: 2
    • Views: 179
    21st February 2017, 13:04 Go to last post
  17. [SOLVED] Procedure with sequential process edge detection

    Started by nsgil85, 21st February 2017 09:01
    • Replies: 7
    • Views: 232
    21st February 2017, 13:01 Go to last post
  18. When is the VHDL pointer useful?

    Started by matrixofdynamism, 20th February 2017 16:45
    • Replies: 5
    • Views: 347
    21st February 2017, 10:41 Go to last post
  19. fpga for dsp in vhdl language

    Started by maryam2015, 19th January 2017 11:34
    • Replies: 10
    • Views: 653
    21st February 2017, 06:00 Go to last post
  20. Help in verilog for MIPS design

    Started by Adnan86, 6th February 2017 10:21
    • Replies: 7
    • Views: 495
    21st February 2017, 05:55 Go to last post
  21. How to see XDC Templates in Vivado 2016.1 ?

    Started by msdarvishi, 21st February 2017 01:12
    • Replies: 1
    • Views: 268
    21st February 2017, 02:37 Go to last post
    • Replies: 4
    • Views: 315
    20th February 2017, 08:11 Go to last post
  22. Clock Synchronization with FPGA

    Started by rayhh27, 7th February 2017 13:58
    • Replies: 7
    • Views: 537
    19th February 2017, 09:14 Go to last post
  23. Image rotation algorithm - Forward vs Backward mapping

    Started by shaiko, 17th February 2017 19:53
    • Replies: 4
    • Views: 375
    18th February 2017, 03:25 Go to last post