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Threads 301 to 330 of 22009

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. TimeQuest analysis for pulse width

    Started by mahmood.n, 13th July 2017 11:18
    • Replies: 1
    • Views: 567
    13th July 2017, 19:11 Go to last post
  2. question about CMT of the spartan 6

    Started by matin-kh, 12th July 2017 12:20
    • Replies: 1
    • Views: 578
    13th July 2017, 02:24 Go to last post
  3. What FPGA logic do constants consume

    Started by shaiko, 11th July 2017 22:20
    • Replies: 7
    • Views: 937
    12th July 2017, 17:13 Go to last post
  4. Strange simulator behavior for code in Verilog

    Started by Gizmotoy, 10th July 2017 23:34
    • Replies: 9
    • Views: 858
    11th July 2017, 22:21 Go to last post
    • Replies: 14
    • Views: 1,418
    11th July 2017, 17:56 Go to last post
  5. Implementing Look up table in FPGA

    Started by beginner_EDA, 5th July 2017 15:55
    • Replies: 13
    • Views: 1,133
    11th July 2017, 13:51 Go to last post
  6. Synthesis: Check_Design Report too many warnings

    Started by Johannah, 13th June 2017 08:48
    • Replies: 6
    • Views: 991
    11th July 2017, 08:40 Go to last post
    • Replies: 2
    • Views: 390
    10th July 2017, 18:21 Go to last post
  7. signal value conflict in VHDL

    Started by mahmood.n, 9th July 2017 12:03
    • Replies: 16
    • Views: 1,141
    10th July 2017, 16:49 Go to last post
  8. Difference b/w asynchronous Vs synchronous FIFO

    Started by rac70, 7th July 2017 12:53
    • Replies: 5
    • Views: 687
    10th July 2017, 10:39 Go to last post
  9. getting and passing data in CPLD

    Started by linam, 7th July 2017 09:38
    • Replies: 3
    • Views: 716
    9th July 2017, 10:36 Go to last post
  10. PCIe-PCI bridge Soft IP core in FPGA

    Started by fpga93, 7th July 2017 10:23
    • Replies: 0
    • Views: 330
    7th July 2017, 10:23 Go to last post
  11. Proper 10-bit 100mhz parallel ADC interface

    Started by asdf44, 7th July 2017 01:55
    • Replies: 3
    • Views: 561
    7th July 2017, 06:59 Go to last post
    • Replies: 6
    • Views: 678
    6th July 2017, 19:06 Go to last post
    • Replies: 0
    • Views: 335
    6th July 2017, 14:29 Go to last post
  12. JTAG pin constarints in VC707

    Started by prakashgudala, 6th July 2017 10:59
    • Replies: 1
    • Views: 311
    6th July 2017, 14:24 Go to last post
  13. [SOLVED] Unable to understand timing diagram of a digital ckt

    Started by hobbyiclearner, 5th July 2017 10:11
    • Replies: 8
    • Views: 626
    6th July 2017, 11:20 Go to last post
  14. How to avoid using clock trees in Zynq FPGAs?

    Started by msdarvishi, 15th June 2017 00:35
    • Replies: 7
    • Views: 1,143
    6th July 2017, 04:48 Go to last post
    • Replies: 1
    • Views: 565
    6th July 2017, 00:59 Go to last post
  15. matrix array from instantiations

    Started by nizdom, 21st June 2017 10:33
    • Replies: 7
    • Views: 723
    5th July 2017, 22:51 Go to last post
    • Replies: 3
    • Views: 478
    5th July 2017, 17:40 Go to last post
  16. doubt in fpga terminal program

    Started by dipin, 21st June 2017 15:12
    • Replies: 9
    • Views: 1,026
    5th July 2017, 14:31 Go to last post
  17. Matrix array inside a for loop VHDL

    Started by nizdom, 29th June 2017 14:41
    • Replies: 18
    • Views: 1,698
    4th July 2017, 16:34 Go to last post
  18. array type range constraint

    Started by Binome, 4th July 2017 08:38
    • Replies: 2
    • Views: 357
    4th July 2017, 11:07 Go to last post
    • Replies: 2
    • Views: 538
    4th July 2017, 09:09 Go to last post
  19. [SOLVED] VHDL 1 D Kalman Filter

    Started by abimann, 8th January 2017 10:58
    • Replies: 9
    • Views: 1,132
    3rd July 2017, 13:25 Go to last post
  20. reading from w5300 registers

    Started by farzaneh_2561, 28th June 2017 08:22
    • Replies: 7
    • Views: 1,045
    1st July 2017, 07:25 Go to last post
    • Replies: 0
    • Views: 318
    30th June 2017, 16:11 Go to last post