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Threads 301 to 330 of 21843

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] vhdl coding for pipo and testbench

    Started by marzhan, 28th April 2017 08:43
    • Replies: 4
    • Views: 439
    28th April 2017, 23:13 Go to last post
    • Replies: 3
    • Views: 284
    28th April 2017, 16:06 Go to last post
    • Replies: 3
    • Views: 367
    28th April 2017, 11:52 Go to last post
  2. Implementing logic in ram

    Started by NovNov, 25th April 2017 16:10
    • Replies: 10
    • Views: 525
    27th April 2017, 23:23 Go to last post
  3. Ram accessing through VHDL code.

    Started by abhijithr1, 27th April 2017 08:27
    • Replies: 2
    • Views: 257
    27th April 2017, 11:49 Go to last post
    • Replies: 1
    • Views: 228
    27th April 2017, 07:05 Go to last post
    • Replies: 0
    • Views: 205
    27th April 2017, 05:09 Go to last post
  4. Flip Flop Memory in FPGA: Read Write Ports

    Started by dzafar, 27th April 2017 00:38
    • Replies: 1
    • Views: 245
    27th April 2017, 01:04 Go to last post
  5. Generate 40 Hz from 44MHz clock

    Started by dhan_pow, 21st April 2017 05:33
    • Replies: 3
    • Views: 361
    26th April 2017, 16:16 Go to last post
  6. using if statement in verilog

    Started by emerson_11, 21st April 2017 05:22
    • Replies: 7
    • Views: 537
    26th April 2017, 14:20 Go to last post
  7. [moved] Dual MicroBlaze design in Xilinx EDK 10.1

    Started by roshan12, 19th April 2017 05:39
    • Replies: 5
    • Views: 621
    26th April 2017, 07:25 Go to last post
  8. [SOLVED] vhdl FSM lockout, lazy approach to fix

    Started by wesleytaylor, 24th April 2017 14:13
    • Replies: 7
    • Views: 491
    25th April 2017, 23:27 Go to last post
  9. CD4033 higher input frequency variant?

    Started by neazoi, 25th April 2017 12:24
    • Replies: 4
    • Views: 325
    25th April 2017, 22:15 Go to last post
  10. axi4-stream inetrface

    Started by viyaaloth, 25th April 2017 06:09
    • Replies: 2
    • Views: 286
    25th April 2017, 08:35 Go to last post
    • Replies: 4
    • Views: 355
    25th April 2017, 05:30 Go to last post
  11. Stereo AC97 Audio Codec

    Started by Tarunfpga1, 23rd April 2017 09:48
    • Replies: 6
    • Views: 632
    24th April 2017, 19:41 Go to last post
  12. VHDL 2x16 LCD module

    Started by rmadd95, 20th April 2017 21:01
    • Replies: 4
    • Views: 456
    24th April 2017, 15:44 Go to last post
  13. understanding the memory specifications

    Started by sai_shashi, 23rd April 2017 06:42
    • Replies: 2
    • Views: 249
    23rd April 2017, 07:54 Go to last post
    • Replies: 1
    • Views: 246
    23rd April 2017, 07:52 Go to last post
  14. [SOLVED] If or else if? Which is better?

    Started by FecP, 22nd April 2017 12:26
    • Replies: 3
    • Views: 423
    22nd April 2017, 19:58 Go to last post
  15. Formal port/generic is not declared error - VHDL

    Started by arve9066, 21st April 2017 19:38
    • Replies: 3
    • Views: 523
    21st April 2017, 22:44 Go to last post
  16. VHDL - generate signals from other signals

    Started by arve9066, 14th April 2017 18:27
    • Replies: 8
    • Views: 738
    21st April 2017, 19:58 Go to last post
    • Replies: 2
    • Views: 323
    20th April 2017, 19:15 Go to last post
  17. How FPGAs are refreshing the logic

    Started by Vlad., 20th April 2017 09:14
    • Replies: 2
    • Views: 356
    20th April 2017, 14:31 Go to last post
  18. [SOLVED] Enumeration of range type - vhdl

    Started by wesleytaylor, 7th April 2017 18:13
    • Replies: 2
    • Views: 443
    20th April 2017, 08:31 Go to last post
    • Replies: 1
    • Views: 232
    20th April 2017, 08:29 Go to last post
  19. Difference between FIFO and buffer

    Started by viyaaloth, 20th April 2017 07:11
    • Replies: 1
    • Views: 229
    20th April 2017, 08:21 Go to last post
  20. Xilinx: 7 series FPGA Transreceiver

    Started by vivekvlsi, 19th April 2017 21:20
    • Replies: 3
    • Views: 397
    20th April 2017, 01:34 Go to last post
  21. Suggestion of relay for controlling FPGA

    Started by junly, 18th April 2017 11:17
    • Replies: 3
    • Views: 395
    19th April 2017, 07:54 Go to last post