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Threads 301 to 330 of 21730

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Problems with Verilog bit array.....

    Started by PhillHS, 20th March 2017 02:23
    • Replies: 3
    • Views: 288
    24th March 2017, 06:57 Go to last post
  2. Xilinx Spartan 6 - Use PLL to create 1 MHz clock

    Started by pigtwo, 21st March 2017 03:29
    • Replies: 17
    • Views: 689
    23rd March 2017, 23:10 Go to last post
    • Replies: 5
    • Views: 393
    23rd March 2017, 15:05 Go to last post
  3. Srio ipcore. can't simulate when using 3.125g mode.

    Started by bravoegg, 21st March 2017 12:01
    • Replies: 2
    • Views: 293
    22nd March 2017, 16:01 Go to last post
  4. Manually implementation of a FIR filter in a FPGA.

    Started by flote21, 14th March 2017 17:42
    • Replies: 16
    • Views: 611
    22nd March 2017, 09:36 Go to last post
    • Replies: 16
    • Views: 500
    20th March 2017, 20:56 Go to last post
  5. how to write a verilog code using point form??

    Started by yeppolife92, 17th March 2017 08:38
    • Replies: 7
    • Views: 390
    20th March 2017, 16:14 Go to last post
  6. [SOLVED] MIG FIFO Requirement

    Started by pcmistic, 18th March 2017 15:35
    • Replies: 2
    • Views: 327
    19th March 2017, 12:56 Go to last post
    • Replies: 1
    • Views: 320
    17th March 2017, 10:39 Go to last post
  7. newbie's questions about PAL

    Started by dk_spb, 24th February 2017 17:40
    • Replies: 18
    • Views: 532
    15th March 2017, 10:51 Go to last post
    • Replies: 9
    • Views: 415
    15th March 2017, 10:35 Go to last post
    • Replies: 4
    • Views: 441
    15th March 2017, 10:26 Go to last post
  8. [SOLVED] Verilog counter not counting

    Started by DocJava, 14th March 2017 14:32
    • Replies: 4
    • Views: 352
    14th March 2017, 16:29 Go to last post
  9. Round Robin systemverilog code question

    Started by promach, 14th March 2017 14:45
    • Replies: 1
    • Views: 370
    14th March 2017, 16:10 Go to last post
  10. Failing Timequest path not shown in RTL viewer

    Started by shaiko, 9th March 2017 10:49
    • Replies: 4
    • Views: 302
    13th March 2017, 21:00 Go to last post
  11. FPGA Prototyping of ZSP DSP 900

    Started by velu.plg, 10th March 2017 12:27
    • Replies: 5
    • Views: 343
    13th March 2017, 17:01 Go to last post
  12. VHDL code exercise. Please help!!

    Started by robertocastiglioni, 13th March 2017 01:09
    • Replies: 5
    • Views: 459
    13th March 2017, 16:30 Go to last post
  13. [SOLVED] SPI EEPROM and GPS Receiver

    Started by rayhh27, 10th March 2017 10:33
    • Replies: 1
    • Views: 294
    10th March 2017, 16:52 Go to last post
  14. Native VHDL negation function

    Started by shaiko, 8th March 2017 12:30
    • Replies: 8
    • Views: 413
    9th March 2017, 23:43 Go to last post
  15. how to call decimal values in verilog

    Started by emerson_11, 7th March 2017 11:17
    • Replies: 7
    • Views: 493
    9th March 2017, 19:08 Go to last post
  16. VHDL process fundamentals

    Started by Ripatti, 9th March 2017 13:51
    • Replies: 1
    • Views: 249
    9th March 2017, 14:14 Go to last post
  17. microblaze c code help

    Started by linuscomex, 9th March 2017 12:31
    • Replies: 0
    • Views: 256
    9th March 2017, 12:31 Go to last post
  18. when the "signal will update" in fpga

    Started by chandru4u4, 9th March 2017 06:08
    • Replies: 4
    • Views: 302
    9th March 2017, 11:17 Go to last post
  19. [SOLVED] Mul18x18 Xilinx primitive + modelsim simu

    Started by flote21, 8th March 2017 19:33
    • Replies: 2
    • Views: 316
    9th March 2017, 08:43 Go to last post
  20. FMC104 and VCU118 Compatibility

    Started by sahar8j, 8th March 2017 13:02
    • Replies: 2
    • Views: 222
    9th March 2017, 07:51 Go to last post
  21. module instantiation

    Started by ecasha, 8th March 2017 07:05
    • Replies: 4
    • Views: 339
    8th March 2017, 17:49 Go to last post
  22. The error about ARAM reading

    Started by Kynix, 7th March 2017 09:00
    • Replies: 3
    • Views: 321
    8th March 2017, 03:40 Go to last post
  23. s27 Benchmark circuit

    Started by ecasha, 7th March 2017 15:12
    • Replies: 1
    • Views: 383
    7th March 2017, 16:06 Go to last post